CDC5801 Datasheet, PDF (13/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
MULT0 and/or MULT1
CLKOUT/
CLKOUTB
t(MULT)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 7. MULT Transition Timings
t(ON)
STOPB
t(CLKSETL)
t(CLKON)
(see Note A)
ÎÎÎÎ _CLKOUT/
ÎÎÎÎÎÎÎÎ CLKOUTB
t(STOP)
t(CLKOFF)
(see Note A)
ÎÎÎÎÎÎÎÎÎ
Output Clock
Not Specified
Glitches OK
NOTE A: Vref = VO ± 200 mV
Clock Enabled
and Glitch Free
Clock Output Settled
Within 50 ps of the
Phase Before Disabled
Figure 8. STOPB Transition Timings
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