CDC5801 Datasheet, PDF (10/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
jitter specification over recommended operating free-air temperature range and V_CC (unless
otherwise noted) (continued)
PARAMETER
CLKOUT
t(jitter)
(Divider mode with
phase alignment and
programmable delay
features selected. See
Figure 2.)
50.0 MHz
MULT0:1 = 00
(Divider
ratio = 2)
62.5 MHz
† _{All typical values are at VDD = 3.3 V, TA = 25°C.}
TEST CONDITIONS
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
Cycle-to-cycle (–)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
Cycle-to-cycle (–)
MIN TYP^†
9.0
50
13
35
35
6.5
30
10
26
26
MAX
UNIT
ps
ps
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
t(DC)
tr, tf
Output duty cycle
Output rise and fall times (measured at 20%–80% of
output voltage)
† _{All typical values are at VDD = 3.3 V, TA = 25°C.}
TEST CONDITIONS
See Figure 3
See Figure 5 and Figure 1
MIN TYP^† MAX UNIT
45%
55%
150
350 ps
10
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