CDC5801 Datasheet, PDF (14/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
19.44 MHz
Z = 50 Ω ; Length = L1
Z = 50 Ω
CDCVF2310
Clock Buffer
CLK
3.3 V
3.3 V
3.3 V
CDC5801
VDDREF
P0
REFCLK
VDDP
GNDP
P1
VDDO
GNDO
GND
CLKOUT
LEADLAG
NC
DLYCTRL CLKOUTB
GNDPA
GNDO
VDDPA
VDDPD
STOPB
VDDO
MULT0/DIV0
MULT1/DIV1
PWRDNB
P2
Outputs are Phase Aligned
Between the Two Buffers
3.3 V
20 R
Z = 50 Ω
CDCVF2310
Clock Buffer
CLK
3.3 V
3.3 V
Z = 50 Ω ; Length = L1
Figure 9. Using the CDC5801 Device as a Multiplier by 8 and Aligning Two Different Clocks
14
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265