CC430F613X_12 Datasheet, PDF (47/121 Pages) Texas Instruments – MSP430™ SoC with RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554F – MAY 2009 – REVISED DECEMBER 2011
Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I_(OHmax) = –1 mA, PxDS.y = 0⁽²⁾
V_OH
High-level output voltage,
Reduced Drive Strength⁽¹⁾
I_(OHmax) = –3 mA, PxDS.y = 0⁽³⁾
I_(OHmax) = –2 mA, PxDS.y = 0⁽²⁾
I_(OHmax) = –6 mA, PxDS.y = 0⁽³⁾
I_(OLmax) = 1 mA, PxDS.y = 0⁽²⁾
V_OL
Low-level output voltage,
Reduced Drive Strength⁽¹⁾
I_(OLmax) = 3 mA, PxDS.y = 0⁽³⁾
I_(OLmax) = 2 mA, PxDS.y = 0⁽²⁾
I_(OLmax) = 6 mA, PxDS.y = 0⁽³⁾
I_(OHmax) = –3 mA, PxDS.y = 1⁽²⁾
V_OH
High-level output voltage,
Full Drive Strength
I_(OHmax) = –10 mA, PxDS.y = 1⁽³⁾
I_(OHmax) = –5 mA, PxDS.y = 1⁽²⁾
I_(OHmax) = –15 mA, PxDS.y = 1⁽³⁾
I_(OLmax) = 3 mA, PxDS.y = 1⁽²⁾
V_OL
Low-level output voltage,
Full Drive Strength
I_(OLmax) = 10 mA, PxDS.y = 1⁽³⁾
I_(OLmax) = 5 mA, PxDS.y = 1⁽²⁾
I_(OLmax) = 15 mA, PxDS.y = 1⁽³⁾
V_CC
1.8 V
3.0 V
1.8 V
3.0 V
1.8 V
3V
1.8 V
3V
MIN
MAX
V_CC – 0.25
V_CC – 0.60
V_CC – 0.25
V_CC – 0.60
V_SS
V_SS
V_SS
V_SS
V_CC – 0.25
V_CC – 0.60
V_CC – 0.25
V_CC – 0.60
V_SS
V_SS
V_SS
V_SS
V_CC
V_CC
V_CC
V_CC
V_SS + 0.25
V_SS + 0.60
V_SS + 0.25
V_SS + 0.60
V_CC
V_CC
V_CC
V_CC
V_SS + 0.25
V_SS + 0.60
V_SS + 0.25
V_SS + 0.60
UNIT
V
V
V
V
f_Px.y
Port output frequency
(with load)
C_L = 20 pF, R_L ^{(4) (5)}
V_CC = 1.8 V
PMMCOREVx = 0
V_CC = 3 V
PMMCOREVx = 2
16
MHz
25
f_{Port_CLK} Clock output frequency
C_L = 20 pF⁽⁵⁾
V_CC = 1.8 V
PMMCOREVx = 0
V_CC = 3 V
PMMCOREVx = 2
16
MHz
25
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(4) A resistive divider with 2 × R1 between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L = 20 pF is connected to the output to V_SS.
(5) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.
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