CC430F613X_12 Datasheet, PDF (15/121 Pages) Texas Instruments – MSP430™ SoC with RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554F – MAY 2009 – REVISED DECEMBER 2011
SHORT-FORM DESCRIPTION
Sub-1-GHz Radio
The implemented sub-1-GHz radio module is based on the industry-leading CC1101, requiring very few external
components. Figure 1 shows a high-level block diagram of the implemented radio.
RADIO CONTROL
RF_P
RF_N
LNA
0
90
ADC
ADC
FREQ
SYNTH
PA
RC OSC
BIAS
XOSC
RBIAS
RF_XIN RF_XOUT
Figure 1. Sub-1-GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and
down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic
gain control (AGC), fine channel filtering, demodulation bit/packet synchronization are performed digitally.
The transmitter part is based on direct synthesis of the RF frequency. The frequency synthesizer includes a
completely on-chip LC VCO and a 90 degrees phase shifter for generating the I and Q LO signals to the
down-conversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the
ADC and the digital part.
A memory mapped register interface is used for data access, configuration and status request by the CPU.
The digital baseband includes support for channel configuration, packet handling and data buffering.
For complete module descriptions, see the CC430 Family User's Guide, literature number SLAU259.
Copyright © 2009–2011, Texas Instruments Incorporated
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