CC430F613X_12 Datasheet, PDF (40/121 Pages) Texas Instruments – MSP430™ SoC with RF Core

CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS554F – MAY 2009 – REVISED DECEMBER 2011
www.ti.com
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to V_SS
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS)⁽²⁾
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS⁽²⁾
–0.3 V to 4.1 V
–0.3 V to (V_CC + 0.3 V),
4.1 V Max
–0.3 V to 2.0 V
Input RF level at pins RF_P and RF_N
10 dBm
Diode current at any device terminal
Storage temperature range⁽³⁾, T_stg
Maximum junction temperature, T_J
±2 mA
–55°C to 150°C
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
θ_JA Junction to ambient thermal resistance, still air
Low-K board
High-K board
48 QFN (RGZ)
48 QFN (RGZ)
98°C/W
28°C/W
Thermal Packaging Characteristics CC430F61xx
θ_JA Junction to ambient thermal resistance, still air
Low-K board
High-K board
64 QFN (RGC)
64 QFN (RGC)
83°C/W
26°C/W
Recommended Operating Conditions
V_CC
V_CC
V_CC
V_SS
T_A
T_J
C_VCORE
C_DVCC/
C_VCORE
f_SYSTEM
Supply voltage range applied at all DVCC and AVCC
pins⁽¹⁾ during program execution and flash programming
with PMM default settings. Radio is not operational with
PMMCOREVx = 0, 1.⁽²⁾
PMMCOREVx = 0
(default after POR)
PMMCOREVx = 1
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 2
pins⁽¹⁾ during program execution, flash programming and
radio operation with PMM default settings.⁽²⁾
PMMCOREVx = 3
Supply voltage range applied at all DVCC and AVCC
pins⁽¹⁾ during program execution, flash programming and
radio operation with PMMCOREVx = 2, high-side SVS
level lowered (SVSHRVLx=SVSHRRRLx=1) or high-side
SVS disabled (SVSHE=0).^{(3) (2)}
PMMCOREVx = 2,
SVSHRVLx = SVSHRRRLx = 1
or SVSHE = 0
Supply voltage applied at the exposed die attach VSS and
AVSS pin
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE
Capacitor ratio of capacitor at DVCC to capacitor at
VCORE
PMMCOREVx = 0
(default condition)
Processor (MCLK) frequency⁽⁴⁾ (see Figure 2)
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
MIN NOM MAX UNIT
1.8
3.6 V
2.0
3.6 V
2.2
3.6 V
2.4
3.6 V
2.0
3.6 V
0
–40
–40
470
10
0
0
0
0
V
85 °C
85 °C
nF
8 MHz
12 MHz
16 MHz
20 MHz
(1) It is recommended to power AV_CC and DV_CC from the same source. A maximum difference of 0.3 V between AV_CC and DV_CC can be
tolerated during power up and operation.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation but the core voltage
will still stay within it's limits and is still supervised by the low-side SVS ensuring reliable operation.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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