AMC7823_15 Datasheet, PDF (43/55 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
www.ti.com
SLAS453F – APRIL 2005 – REVISED MARCH 2012
DAC-n Data Registers (n = 0, 1, 2, 3, 4, 5, 6, 7) (see the DAC Operation section)
This register is the input Data Register for DAC-n that buffers the DAC-n Latch Register. The DAC-n output is
updated only when Latch is loaded. Under an asynchronous load (bit SLDA-n = '0' in the DAC Configuration
Register), the value of the DAC-n Data Register is transferred into the Latch immediately after Data Register is
written. If a synchronous load is specified (SLDA-n = '1'), then the DAC-n Latch is loaded with the value of the
DAC-n Data Register only after a synchronous load signal occurs. This signal can be either the internal ILDAC or
the rising edge of an external ELDAC (see DAC Operation and DAC Configuration Register discussions).
Bit 15
MSB Bit 14
X OCH2
X : Don't Care
Bit 13
OCH1
Bit 12
OCH0
Bit 11
DAC1
1
Bit 10
DAC1
0
Bit 9
DAC9
Bit 8
DAC8
Bit 7
DAC7
Bit 6
DAC6
Bit 5
DAC5
Bit 4
DAC4
Bit 3
DAC3
Bit 2
DAC2
Bit 1
DAC1
Bit 0
LSB
DAC0
DAC11–DAC0
(WRITE/READ)
OCH2–OCH0
In a write operation, these data bits are written into the DAC Data-n Register. However, in
a read operation, the data bits are returned from the DAC-n Latch, not from the DAC-n
Data Register.
DAC Address. Read-only. Writing these bits does not cause any change.
The registers are cleared to '0' after power-on or reset. Table 15 summarizes the DAC-n Data Registers.
OCH2
0
0
0
0
1
1
1
1
Table 15. DAC-n Data Registers
OCH1
0
0
1
1
0
0
1
1
OCH0
0
1
0
1
0
1
0
1
ANALOG OUTPUT
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
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