AMC7823_15 Datasheet, PDF (35/55 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
www.ti.com
SLAS453F – APRIL 2005 – REVISED MARCH 2012
The ELDAC pin is an input pin for the external DAC synchronous load signal. The rising edge of ELDAC updates
all DAC-n simultaneously that have the corresponding bit SLDA-n set to '1'.
The AMC7823 has six GPIO pins, GPIO-n (n = 0, 1, 2, 3, 4, 5). Pins GPIO-4 and GPIO-5 are dedicated to
general bidirectional digital I/O signals. The remaining pins (n = 0, 1, 2, 3) are dual-purpose pins, and can be
programmed as either bidirectional GPIO or ALR (out-of-range alarm) indicators. Figure 51 shows the pin
structure of GPIO-4 and GPIO-5. See Figure 52 for the pin structure of GPIO-n (n = 0, 1, 2 and 3).
The bit IOMOD-n (n = 0, 1, 2, 3) in the GPIO register defines the function of these dual-purpose GPIO-n pins
(see Table 8). When the corresponding IOMOD-n bit is cleared to '0', GPIO-n pins are configured as out-of-range
indicators (denoted ALR-0, ALR-1, ALR-2, and ALR-3) for the first four analog inputs being converted. As an out-
of-range indicator, the ALR-n pin is an output whose status is determined by bits ALR-0, ALR-1, ALR-2, and
ALR-3 of the ALR Register. When ALR-n is set to '1', the ALR-n pin is low. When ALR-n is cleared to '0', the
ALR-n pin is in high impedance status. When IOMOD-n is set to '1', the GPIO-n pin works as a general,
bidirectional digital I/O pin.
PIN NAME
GPIO-0
GPIO-1
GPIO-2
GPIO-3
Table 8. GPIO Function
1
GPIO
GPIO
GPIO
GPIO
IOMOD-n
0
ALR-0
ALR-1
ALR-2
ALR-3
When the GPIO-n pin works as general, bidirectional digital I/O, it can receive an input or produce an output.
(See Figure 51 and Figure 52.) When acting as output, its status is determined by the corresponding bit IOST-n
(I/O Status) of the GPIO Register. The output is high impedance when bit IOST-n is set to '1' and is logic low
when bit IOST-n is cleared to '0'. An external pull-up resistor is required when using GPIO-n as output.
When GPIO-n acts as input, the digital value on the pin is acquired by reading the bit IOST-n.
After power-on reset or any forced hardware or software reset, all IOMOD-n and IOST-n bits are set to '1', and all
GPIO pins work as general I/O pins in high impedance status. See the GPIO Register for more detail.
GPIO-n
IOST-n
(when writing IOST-n)
IOST-n
(when reading IOST-n)
ENABLE
Figure 51. Pin Structure of GPIO-4 and GPIO-5
Copyright © 2005–2012, Texas Instruments Incorporated
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