THS8083APZPG4 Datasheet, PDF (41/63 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS 3.3-V Video and Graphics

5.2 Timing Diagram—16-Bit Parallel Mode
This is the ITU−R.BT−601 style mode typically used in YUV operation of the part with a Y analog input connected
to the Ch1 input of the THS8083A, and with Cb and Cr connected to the Ch2 and Ch3 inputs, respectively. The
DATACLK1 output is at the sampling clock frequency and Ch3 remains unused. The output bus B of all channels is
high impedance. The HS_D signal can be used to uniquely identify output data Cb from Cr.
ADCCLK2
DATACLK
CH1_OUTA[7..0]
CH1_OUTB[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
DHS
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
pix 01
pix 02
Cb: From Ch.2 Input
Cr: From Ch.3 Input
7 ADCCLK2 Cycles Latency
tsu(OUT)
th(OUT)
Last Samples From Previous Line
01
02
03
tPLH(OE)
Last Samples From Previous Line 01(Cb)
tPHL(OE)
01(Cr)
03(Cb)
tsu(DHS)
th(DHS)
7 ADCCLK2
Cycles Latency
<DHS_MODE> = 1 −> Width
Equal to Width of HS Input
<DHS_MODE> = 0 −> DHS
Width is 1 ADCCLK2 Period
5−2