THS8083APZPG4 Datasheet, PDF (21/63 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS 3.3-V Video and Graphics

3.7 Output Formatter
This block enables either a 4:4:4 24-bit output or a 4:4:4 48-bit output at half the pixel clock, or a 4:2:2 16-bit output
useful for YUV digitizing (ITU.BT-601 style). In the latter case, an 8-bit port is used for the Y output while a second
8-bit port is used alternately for Cr or Cb. As per ITU BT-601, Cb is the first video data word for each line, as shown
in Figure 2-7.
The first color sample after an incoming HS is Cb. The output signal DHS is synchronized to the first pixel of a line
and can therefore be used to uniquely identify Cb from Cr output data in down-sampled modes.
X
Sampling Format
Y
3 Channels
Cr (R-Y or V)
Y
Cb (or B-Y or U)
Output Formatter Combines Ob
and Cr On Single Output Bus
Cb Cr Cb Cr Cb
2 Channels
YY
t
Y YY
Output Format
On Ch1 Bus A
Output
On Ch2 Bus A
Output
Other Outputs HI-Z
Figure 3−7. Output Formatter
3.8 Power Down
Three power down modes are defined in the I²C power-down register, :
• Chip power down: PWDN_ALL
When PWDN_ALL=1, all analog circuits are powered down except the internal bandgap reference, the
circuit that generates the clamping voltages and the sync reference voltage. All these are kept active for
the composite sync slicer that remains active during power down. The clock frequency of the digital circuitry
is lowered to reduce power consumption when in power down.
• Internal reference power down: PWDN_REF
When PWDN_REF=1, bottom and top references (VREFB, VREFT) on all channels become inputs and
should be externally driven.
• Bandgap reference power down: PWDN_BGAP
When PWDN_BGAP=1, the internal bandgap reference voltage is inactive and terminal VMID should be
externally driven.
Additionally, the DTO circuitry can be disabled:
• DTO power down: DTO_DIS
When DTO_DIS=1, the DTO frequency is lowered to reduce power dissipation. This feature can be
activated when an external sampling clock is used (EXT_ADCCLK).
3−8