THS8083APZPG4 Datasheet, PDF (30/63 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS 3.3-V Video and Graphics

3.11.23 Register Name: DTO_INC_2
MSB
DTO_INC23
DTO_INC22 DTO_INC21 DTO_INC20 DTO_INC19
DTOINC[23..16]:
See register DTO_INC_0
Default: (changed during operation)
3.11.24 Register Name: DTO_INC_3
MSB
DTO_INC31
DTO_INC30 DTO_INC29 DTO_INC28 DTO_INC27
DTO_INC[31..24]:
See register DTO_INC_0.
Default: (changed during operation)
3.11.25 Register Name: DTO_INC_4
MSB
X
X
X
X
X
DTO_INC32:
See register DTO_INC_0.
Default: (changed during operation)
3.11.26 Register Name: SYNC_DETECT
MSB
X
X
X
X
X
NO_SYNC:
Sync detection on HS.
0 = HS present
1 = HS missing
Default: (changed during operation)
3.11.27 Register Name: CLP_CTRL
MSB
CLPSEL
CLP1_EN
CLP1_RG
CLP2_EN
CLPSEL Selects the clamp timing signal
0: internal clamp timing pulse is selected (default)
1: external clamp timing pulse is selected
CLP1_EN: Enables/disables clamping on channel 1
1: enable (default)
0: disable
CLP1_RG: Sets the clamp range for channel 1
1: middle range
0: bottom range (default)
DTO_INC18
Subaddress: 16 (R)
DTO_INC17
LSB
DTO_INC16
DTO_INC26
Subaddress: 17 (R)
DTO_INC25
LSB
DTO_INC24
Subaddress: 18 (R)
LSB
X
X
DTO_INC32
Subaddress: 19 (R)
LSB
X
X
NO_SYNC
CLP2_RG
Subaddress: 20 (R/W)
CLP3_EN
LSB
CLP3_RG
3−17