THS8083APZPG4 Datasheet, PDF (40/63 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS 3.3-V Video and Graphics

5 Parameter Measurement Information
All timing diagrams are shown for operation with internal PLL clock at phase 0, and ADCCLK2 non-inverted and
non-divided-by-2.
5.1 Timing Diagram—24-Bit Parallel Mode
This mode outputs data on the three channels simultaneously in single-pixel mode. DATACLK1 is at the sampling
clock frequency; output bus B remains high-impedance.
ADCCLK2
DATACLK
CH1_OUTA[7..0]
CH1_OUTB[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
DHS
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
pix 01
pix 02
7 ADCCLK2 Cycles Latency
tsu(OUT)
th(OUT)
Last Samples From Previous Line 01
02
Last Samples From Previous Line 01
02
tPLH(OE)
Last Samples From Previous Line 01
tPHL(OE)
tsu(DHS)
th(DHS)
02
7 ADCCLK2
Cycles Latency
<DHS_MODE> = 1 −> Width
Equal to Width of HS Input
<DHS_MODE> = 0 −> DHS
Width is 1 ADCCLK2 Period
5−1