THS8083APZPG4 Datasheet, PDF (14/63 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS 3.3-V Video and Graphics

3 Functional Description
3.1 Analog Channel
The THS8083A contains three identical analog channels that are independently programmable. Each channel
consists of a clamping circuit, a programmable gain amplifier, and an A/D converter.
3.2 Clamping Circuit
The purpose of clamping is to provide the input signal with a known dc-value. Typically, video signals are ac-coupled
into the part. The signal needs to be level-shifted to fall in the reference voltage range (VREFB...VREFT) of the A/D
converter. By supplying a programmable clamp, the user can shift the input signal with respect to the A/D range. This
has the same effect as keeping the input signal constant and applying offset to both A/D reference voltages while
keeping the VREFT−VREFB difference equal. However, no external adjustments are needed with this
implementation.
For video, the clamping circuit can only be active during the non-active video portion of each line to avoid changes
in brightness along the line. Clamping is done during the horizontal blanking interval, either on the back porch of sync
or during the sync tip (in the case of a sync present on at least one of the video channels). If HS is carried on a separate
line, as is typically the case for PC graphics, clamping is done during blanking. When the Y or G input channel contains
an embedded sync, then alternatively clamping can be done during the sync-tip or during the front or back porch of
sync. Only clamping during front- or back-porch of sync is supported on the THS8083A, since it is expected that the
input signal level during clamping, of which position and width are determined by the clamp timing pulse (as shown
later) corresponds to the blanking level. Since the blanking level for RGB type inputs corresponds to a low output code
of the A/D, it makes sense to center the clamp range around an A/D output code of 0. The user can adjust this level
up or down, symmetrically around 0. If the clamping is set such that the blanking level corresponds to a level below
0, the A/D output is clipped at code 0.
CLP
Reference Level
VIN
CC
PGA 1
PGA 2
8
ADC
Bottom/Mid
Reference Level
Offset
DAC
6
Clamp DAC
8
Clamp Control
PGA Gain Control
Figure 3−1. Analog Channel Architecture
3−1