CDC7005 Datasheet, PDF (4/29 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004
SPI control interface
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device.
It consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide registers,
which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must
have 32 bits, starting with MSB first. Each word can be written separately. Word 0, word 1, and word 2 are user
programmable; however, word 3 is reserved for factory test purposes only. There is no need to program word 3
unless it has to be filled with zeros. The transfer is initiated with the falling edge of CTRL_LE; as long as
CTRL_LE is high, no data can be transferred. During CTRL_LE, low data can be written. The data has to be
applied at CTRL_DATA and has to be stable before the rising edge of CTRL_CLK. The transmission is finished
by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the new word is asynchronously transferred
to the internal register (e.g., N, M, P, ...). Each word has to be separately transmitted by this procedure.
t4
t3
CTRL_CLK
th2
tsu1
CTRL_DATA Bit31 (MSB)
Bit30
Bit2
Bit1
Bit0
CTRL_LE
t7
tsu5
tsu6
Figure 1. Timing Diagram SPI Control Interface
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