CDC7005 Datasheet, PDF (15/29 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004
device characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN TYP^†
MAX UNIT
Overall
ICC
Supply current (see Note 7)
fVCXO = 245 MHz, fREF_IN = 30 MHz,
VCC = 3.6 V, AVCC = 3.6 V,
fPFD = 240 kHz, ICP = 2 mA,
(see Note 9 and Note 12)
230
265 mA
ICCPD
tpho
Power-down current
Phase offset (REF_IN to Y output)
(see Note 8)
fIN = 0 MHz, VCC = 3.6 V,
AVCC = 3.6 V, VI = 0 V or VCC
VREF_IN = VCC/2,
Crossing point of Y, See Figure 12
100
−150
300 µA
150 ps
LVCMOS
VIK
LVCMOS input voltage
VCC = 3 V, II = –18 mA
II
LVCMOS input current
VI = 0 V or VCC, VCC = 3.6 V
IIH
LVCMOS input current for NPD,
NRESET
VI = VCC, VCC = 3.6 V
−1.2
V
±5 µA
5 µA
IIL
LVCMOS input current for NPD,
NRESET
VI = 0 V, VCC = 3.6 V
−15
−35 µA
VOH
VOL
CI
CI
LVCMOS high-level output voltage
LVCMOS low-level output voltage
Input capacitance at REF_IN
Input capacitance at CTRL_LE,
CTRL_CLOCK, CTRL_DATA
IOH = −12 mA, VCC = 3 V
IOL = 12 mA, VCC = 3 V
VI = 0 V or VCC
VI = 0 V or VCC
2.1
2
2
V
0.55
V
pF
pF
tdetectREF
Frequency detect time until
STATUS_REF is valid
fREF_IN = 3.5 MHz
5
µs
Frequency detect time until
tdetectVCXO _{STATUS_VCXO is valid}
fVCXO_IN = 10 MHz
5
µs
LVPECL
VINPP
VIC
Input amplitude LVPECL
Common-mode input voltage
LVPECL
(VVCXO_IN −VVCXO_INB), See Note11
0.5
V_CC−2
1.3
V
V_CC−0.4
V
II
LVPECL input current
VI = 0 V or VCC
±100 µA
IOZ
LVPECL output current 3-state
VO = 0 V or VCC−0.8 V
20 µA
VOH
LVPECL high-level output voltage
See Note 9
V_CC−1.18
V_CC−0.81
V
VOL
LVPECL low-level output voltage
See Note 9
V_CC−1.98
V_CC−1.55
V
|VOD|
Differential output voltage
10 ≤ fOUT ≤ 800 MHz, See Figure 6
500
mV
† _{All typical values are at VCC = 3.3 V, temperature = 25°C.}
NOTES: 7. For ICC over frequency see Figure 5.
8. This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M
and VCXO delay N).
9. Outputs are terminated through a 50-Ω resistor to VCC − 2 V.
10. The tsk(o) specification is only valid for equal loading of all outputs.
11. VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of
100 mV.
12. All output switching at default divider ratios.
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