CDC7005 Datasheet, PDF (12/29 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004
functional description of the logic (continued)
Power Up or Reset
and REF_IN Active
STATE 1: PRE LOCK
Normal Operation VCXO_ IN
Synchronizes with REF_IN
Valid Ref. Frequency
Detected (f > 3.5 MHz)
Five Coherent Cycles
Lock Detect
STATE 3: HOLD OPERATION
CP is in 3-State
REF_IN Missing
STATE 2: HOLD CTRL
REF_IN is Sensed by
VCXO_IN
NOTES: A. For proper hold functionality, the counter M and counter N need to have the same divider ratio. The hold functionality is triggered
by the first missing REF_IN cycle. It is disabled in default mode (bit 2 of word 2 = 0).
B. While the device is in frequency hold mode, a possible leakage current caused by the external filter and VCXO may change the
VCXO control voltage, therefore changing the VCXO frequency. To keep the frequency drift as low as possible, a low leakage current
filter design is recommended or the number of the disrupted / missing REF_IN clock cycles should be kept low (< 100).
Figure 3. State Machine Operation
REF_IN Clock Fed Through
the M Divider and M Delay
t(lockdetect)
VCXO_IN Clock Fed Through
the N Divider and N Delay
NOTE: If the rising edge of REF_IN clock and VCXO_IN clock for PFD are inside the lock detect window (t(lockdetect)) for at least five successive
input clock periods, then the PLL is considered to be locked. In this case, the STATUS_LOCK output is set to high level. The size of the
lock detect window is programmable via the SPI control logic (bit 6 and 7 of word 2). (See Table 8)
Figure 4. Lock Detect Window
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