CDC7005 Datasheet, PDF (3/29 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
GND
B2, B3, B4,
B5, B6, B7,
B8, C2, D2,
D3, D4, D5,
D6, E2, F2,
F3, F4, F5, F6
Ground
Ground
AVCC
C3, C4, C5,
C6, C7
Power 3.3-V analog power supply
CP_OUT
A4
O
Charge pump output
CTRL_LE
A1
I
LVCMOS input, control load enable for serial programmable interface (SPI), with hysteresis
CTRL_CLK
A2
I
LVCMOS input, serial control clock input for SPI, with hysteresis
CTRL_DATA
A3
I
LVCMOS input, serial control data input for SPI, with hysteresis
I_REF
C1
O
Current path for the external reference resistor (12 kΩ ±1%) to support an accurate charge
pump current; optional. Do not use any capacitor across this resistor to prevent noise
coupling via this node. If internal 12 kΩ is selected(default setting), this pin can be left
open.
NPD
H1
I
LVCMOS input, asynchronous power down (PD) signal active on low. Switches all current
sources off, resets all dividers to default values and 3-states all outputs, has internal
150-kΩ pullup resistor
NRESET
H8
I
LVCMOS input, asynchronous reset signal active on low. Resets the counter of all dividers
to zero keeping its divider values the same. It has an internal 150-kΩ pullup resistor. Yx
outputs are switched low during reset.
REF_IN
B1
I
LVCMOS reference clock input
OPA_IN
A5
I
Inverting input of the op amp, see Note 1
OPA_OUT
A7
O
Output of the op amp, see Note 1
OPA_IP
A6
I
Noninverting input of the op amp, see Note 1
STATUS_LOCK
A8
O
This pin is high if the PLL lock definition is valid. PLL lock definition means the rising edge
of REF_IN clock and VCXO_IN clock for PFD are inside the lock detect window for at least
five successive input clock cycles. If the rising edge of REF_IN clock and VCXO_IN clock
are out of the selected lock detect window, this pin will be low, but it does not refer to the
real lock condition of the PLL. See Table 8 and Figure 4.
STATUS_REF
C8
O
LVCMOS output provides the status of the reference input (frequencies above 3.5 MHz are
interpreted as valid clocks, active high)
STATUS_VCXO
D8
O
LVCMOS outputs provides the status of the VCXO input (frequencies above 10 MHz are
interpreted as valid clocks, active high)
VCC
D7, E3, E4,
E5, E6, E7,
E8, F7, G2,
G3, G4, G5,
G6, G7
Power 3.3-V supply
VCXO_IN
D1
I
VCXO LVPECL input
VCXO_INB
E1
I
Complementary VXCO LVPECL input
Y[0:4]
F1, H2, H4,
H6, G8
O
LVPECL output
Y[0:4]B
G1, H3, H5,
H7, F8
O
Complementary LVPECL output
NOTE 1: If the internal operational amplifier is not used, these pins can be left open.
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