THS7303 Datasheet, PDF (39/43 Pages) Texas Instruments – 3-Channel Low Power Video Amplifier with I2C Control, Selectable Filters, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7303
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Step 4
I²C Write Channel Address (Master)
SLOS479 – OCTOBER 2005
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I²C Acknowledge (Slave)
A
Step 6
I²C Write Data (Master)
7
Data
6
Data
5
Data
4
Data
3
Data
2
Data
1
Data
0
Data
Where Data is determined by the values shown in Table 3.
Step 7
9
I²C Acknowledge (Slave)
A
Step 8
0
I²C Stop (Master)
P
For Step 6, an example of the proper bit control for selecting Input B of the MUX, a 720p Y’ channel signal with
AC-STC lowest line tilt and with the shortest sync filter is 1111 0101.
EXAMPLE – READING FROM THE THS7303
The read operation consists of two phases. The first phase is the address phase. In this phase, an I²C master
initiates a write operation to the THS7303 by generating a start condition (S) followed by the THS7303 I²C
address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
THS7303, the master presents the sub-address (channel) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I²C master initiates a read operation to the THS7303 by
generating a start condition followed by the THS7303 I²C address (as shown below for a read operation), in MSB
first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the THS7303, the I²C master
receives one byte of data from the THS7303. After the data byte has been transferred from the THS7303 to the
master, the master generates a not acknowledge followed by a stop. Similar to the Write function, to read all
channels Steps 1 through 11 must be repeated for each and every channel desired.
THS7303 Read Phase 1:
Step 1
0
I²C Start (Master)
S
Step 2
I²C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I²C-A1 and I²C-A0 pins being tied to either Vs+ or GND.
Step 3
9
I²C Acknowledge (Slave)
A
Step 4
I²C Read Channel Address (Master)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I²C Acknowledge (Slave)
A
Step 6
0
I²C Start (Master)
P
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