THS7303 Datasheet, PDF (37/43 Pages) Texas Instruments – 3-Channel Low Power Video Amplifier with I2C Control, Selectable Filters, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7303
www.ti.com
SLOS479 – OCTOBER 2005
APPLICATION INFORMATION (continued)
controlled by the Logic levels appearing on the I²C-A1 and I²C-A0 pins. The I²C-A1 and I²C-A0 address inputs
can be connected to V_S+ for Logic 1, GND for Logic 0, or it can be actively driven by TTL/CMOS logic levels. The
device address is set by the state of these pins and is not latched. Thus, a dynamic address control system can
be used to incorporate several devices on the same system. Up to four THS7303 devices can be connected to
the same I²C-Bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7303
Bit 7 (MSB)
0
0
0
0
0
0
0
0
Bit 6
1
1
1
1
1
1
1
1
Table 1. THS7303 Slave Addresses
FIXED ADDRESS
Bit 5
0
0
0
0
0
0
0
0
Bit 4
1
1
1
1
1
1
1
1
Bit 3
1
1
1
1
1
1
1
1
SELECTABLE WITH
ADDRESS PINS
Bit 2 (A1)
Bit 1 (A0)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
READ/WRITE
BIT
Bit 0
0
1
0
1
0
1
0
1
Channel Selection Register Description (Subaddress)
The THS7303 operates using only a single byte transfer protocol similar to Figure 74 and Figure 76. The internal
subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required
to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired, then
the master has to cycle through all the subaddresses (channels) one at a time, see the example section –Writing
to the THS7303 for the proper procedure of writing to the THS7303.
During a read cycle, the THS7303 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the example section –Reading from the THS7303 for the
proper procedure on reading from the THS7303.
On power up, the THS7303 registers are in a random state from part-to-part. It remains in this random state until
a valid write sequence is made to the THS7303. A total of 9 bytes of data completely configures all channels of
the THS7303. As such, configuring the THS7303 should be done on power-up of the system. Note that one such
random state (acknowledge state) can be engaged. To circumvent this state, have one SCL cycle run, and the
acknowledge state disengages.
Table 2. THS7303 Channel Selection Register Bit Assignments
REGISTER NAME
Channel 1
Channel 2
Channel 3
BIT ADDRESS
(b7b6b5....b0)
0000 0001
0000 0010
0000 0011
Channel Register Bit Descriptions
Each bit of the sub-address (channel selection) control register as described above allows the user to individually
control the functionality of the THS7303. The benefit of this process allows the user to control the functionality of
each channel independent of the other channels. The bit description is decoded in Table 3.
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