THS7303 Datasheet, PDF (35/43 Pages) Texas Instruments – 3-Channel Low Power Video Amplifier with I2C Control, Selectable Filters, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

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APPLICATION INFORMATION (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 71. I²C Bit Transfer
THS7303
SLOS479 – OCTOBER 2005
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
SCL From
Master
1
2
Acknowledge
8
9
S
Start
Condition
Figure 72. I²C Acknowledge
Clock Pulse for
Acknowledgement
SCL
12 3 4 5 6 78 9 123 4 5 67 8 9
SDA
MSB
Acknowledge
Slave Address
Data
Stop
Acknowledge
Figure 73. I²C Address and Data Cycles
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 74 and Figure 75.
Note that the THS7303 does not allow multiple write transfers to occur. See example section – Writing to the
THS7303 for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
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