THS7303 Datasheet, PDF (30/43 Pages) Texas Instruments – 3-Channel Low Power Video Amplifier with I2C Control, Selectable Filters, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7303
SLOS479 – OCTOBER 2005
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APPLICATION INFORMATION (continued)
The internal resistor values were chosen to optimize the system while using the 47-µF and 33-µF capacitors and
to approximate the performance of a single 330-µF capacitor. These capacitors can be a different value if
desired, but the characteristics of the system are altered accordingly. For example, if 22-µF capacitors is used for
both sections, then there are increases in line tilt and field tilt. But, for some systems this may be considered
acceptable such as 720p Y' signals with the associated faster line rates. Using larger values, such as 68 µF and
47 µF respectively, decreases field time distortion even further approaching performance of a single 470-µF
capacitor.
It is important to note that the dc gain is about 2.55 V/V. Thus, if the input has a dc bias, the output dc bias is
2.55 times the input. For example, this results in an output bias point of 355 mV for the dc + 135 mV shift.
Additionally, if the ac bias input mode is selected, the dc operating point is Vs/4 X 2.55, or 2.1 V with 3.3-V
supply and 3.2 V with 5-V supply. This additional offset should not hinder the performance of the THS7303 as
there is still plenty of voltage headroom between the dc operating point and the rail-to-rail output capability.
One possible concern about this configuration is the low frequency gain enhancement may cause saturation of
the signal when low power supply voltages - such as 3 V - are used. Thus, the internal resistors were chosen to
minimize the low frequency gain such that saturation is minimized. Other SAG correction parts have much higher
low frequency gain (10 dB or higher), which when coupled with low power supply voltages, can easily create
clipping on the output of the amplifier both dynamically and at dc. Other SAG correction parts do not use a
resistor in series with the SAG pin. Neglecting this resistor can result in a large Q enhancement causing possible
saturation issues. These systems typically require much larger capacitor values to minimize this problem which
ultimately minimizes the benefits of SAG correction.
Figure 67 shows a SAG corrected configuration for the THS7303. If a S-Video chroma channel is being
configured, there is no reason for SAG correction as the coupling capacitor is typically small at 0.1 µF. Thus,
tying the output pin directly to the SAG output pin is recommended along with a 0.1-µF capacitor.
3.3 V
DAC /
Y’
Encoder
(THS8200)
HDTV
480i
576i
P’_B
480p
576p
720p
1080i
P’_R
1080p
Y’
P’_B
P’_R
R
R
R
0.1 mF
75 W
1 mF
75 W
1 mF
75 W
DC + 135 mV
1 _NC
NC 20
2 CH.1 IN A CH.1 OUT 19
DC + 135 mV
*
3 _{CH.2 IN A} CH. 1 SAG 18
DC + 135 mV
4 _{CH.3 IN A} CH.2 OUT 17
AC STC
*
5 _{CH.1 IN B} CH. 2 SAG 16
AC Bias
6 CH.2 IN B CH.3 OUT 15
AC Bias
*
7 _{CH.3 IN B} CH. 3 SAG 14
8 I2C-A1
SCL 13
9 I2C-A0
SDA 12
10 _GND
VS+ ¹¹
0.01 mF
47 mF
+
33 mF
+
47 mF
+
33 mF
+
47 mF
+
33 mF
+
Y’
75 W ^Out
P’_B
75 W ^Out
P’_R
75 W ^Out
+Vs
+_{100 mF}
2
IC
Controller
* (See Note A)
75 W
75 W
75 W
External
Input
A. If the SAG correction capacitors are more than 15 mm from the THS7313, add a 0.01µF capacitor as shown.
Figure 67. Typical Y'P'_BP'_R System Driving SAG Corrected AC-Coupled Video Lines
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