THS7303 Datasheet, PDF (38/43 Pages) Texas Instruments – 3-Channel Low Power Video Amplifier with I2C Control, Selectable Filters, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

THS7303
SLOS479 – OCTOBER 2005
Table 3. THS7303 Channel Register Bit Decoder Table
BIT
(MSB)
7, 6
5
4,3
2, 1, 0
(LSB)
FUNCTION
STC Low Pass Filter Selection
Input MUX Selection
Low-Pass Filter
Frequency Selection
Input Bias Mode Selection and
Disable Control
BIT
VALUE(S)
00
01
10
11
0
1
00
01
10
11
000
001
010
011
100
101
110
111
RESULT
500-kHz Filter – Useful for 9-MHz Video LPF
2.5-MHz Filter – Useful for 16-MHz Video LPF
5-MHz Filter – Useful for 35-MHz/Bypass Video LPF
5-MHz Filter – Useful for 35-MHz/Bypass Video LPF
Input A Select
Input B Select
9-MHz LPF – Useful for SDTV, S-Video, 480i/576i
16-MHz LPF – Useful for EDTV 480p/576p and VGA
35-MHz LPF – Useful for 720p, 1080i, and SVGA/XGA
Bypass LPF – Useful for 1080p and SXGA/UXGA
Disable Channel – Conserves Power
Channel On – Mute Function – No Output
Channel On – DC Bias Select
Channel On – DC Bias + 135 mV Offset Select
Channel On – AC Bias Select
Channel On – Sync Tip Clamp with Low Bias
Channel On – Sync Tip Clamp with Mid Bias
Channel On – Sync Tip Clamp with High Bias
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Bits 7 (MSB) and 6 – Controls the AC-Sync Tip Clamp Low Pass Filter function. If AC-STC mode is not used,
this function is ignored.
Bit 5 – Controls the input MUX of the THS7303.
Bits 4 and 3 – Controls the 5^th order low pass filter –3 dB corner frequency or the bypass mode of operation.
Bits 2, 1, and 0 (LSB) – Selects the input biasing of the THS7303 and the power-savings function. When sync-tip
clamp is selected, the dc input sink bias current is also selectable.
EXAMPLE – WRITING TO THE THS7303
The proper way to write to the THS7303 is illustrated as follows:
An I²C master initiates a write operation to the THS7303 by generating a start condition (S) followed by the
THS7303 I²C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the THS7303, the master presents the subaddress (channel) it wants to write
consisting of one byte of data, MSB first. The THS7303 acknowledges the byte after completion of the
transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7303
acknowledges the byte. The I²C master then terminates the write operation by generating a stop condition
(P). Note that the THS7303 does not support multi-byte transfers. To write to all three channels – or registers
– this procedure must be repeated for each register one series at a time (i.e., repeat steps 1 through 8 for
each channel).
Step 1
0
I²C Start (Master)
S
Step 2
I²C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I²C-A1 and I²C-A0 pins being tied to either Vs+ or GND.
Step 3
9
I²C Acknowledge (Slave)
A
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