TL16PNP550A Datasheet, PDF (36/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
D Bit 2: Bit 2 is the trailing edge of ring indicator (TERI) detector. This bit indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
D Bit 3: Bit 3 is the change in data carrier detect (∆ DCD) indicator. This bit indicates that the DCD input to
the chip has changed state since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
D Bit 4: Bit 4 is the complement of the clear-to-send (CTS) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (RTS).
D Bit 5: Bit 5 is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (DTR).
D Bit 6; Bit 6 is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this bit
is equivalent to the MCR bit 2 (OUT1).
D Bit 7: Bit 7 is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCR bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that receives a clock input generated by the prescalar block
in the range between 1.833 and 22 MHz and divides it by a divisor in the range between 1 and (2¹⁶ –1). The
output frequency of the baud generator is sixteen times (16 ×) the baud rate. The formula for the divisor is:
divisor # = clock frequency generated by the prescalar block ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure correct operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 19 illustrates the use of the baud generator with a crystal frequency of 22 MHz and a prescalar divisor
of 12. Refer to Figure 20 for an example of a typical clock circuit.
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