TL16PNP550A Datasheet, PDF (28/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers. These
registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in
Table 13.
Table 13. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0
2
2
3
4
5
6
7
0 DLAB = 1 1 DLAB = 1
Receiver Transmitter
Bit
Buffer
Holding
Interrupt
No. _Register
Register
Enable
Interrupt
Ident.
Register
FIFO
Control
Register
Line
Control
Modem
Control
(Read
(Write
Register
(Read
(Write
Register Register
Only)
Only)
Only)
Only)
RBR
THR
IER
IIR
FCR
LCR
MCR
Line
Status
Register
LSR
Modem
Status
Register
Scratch
Register
MSR
SCR
Divisor
Latch
(LSB)
DLL
Latch
(MSB)
DLM
0 Data Bit 0† Data Bit 0
1
Data Bit 1
Data Bit 1
Enable
Received
Data
Available
Interrupt
(ERBI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
0 If
Interrupt
Pending
Interrupt
ID
Bit 1
FIFO
Enable
Receiver
FIFO
Reset
Word
Length
Select
Bit 0
(WLS0)
Word
Length
Select
Bit 1
(WLS1)
Data
Terminal
Ready
(DTR)
Request
to Send
(RTS)
Data
Ready
(DR)
Delta
Clear
to Send
(∆CTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(∆DSR)
Bit 0
Bit 1
Bit 0
Bit 1
Bit 8
Bit 9
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
Parity
Error
(PE)
Trailing
Edge of
Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
3
Data Bit 3
Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 3‡
Reserved
Parity
Enable
(PEN)
OUT2
UART
Interrupt
Enable§
Framing
Error
(FE)
Delta
Data
Carrier
Detect
(∆DCD)
Bit 3
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4
Bit 4
Bit 12
5
Data Bit 5
Data Bit 5
0
Flow
Transmitter
Data
0
Reserved
Stick
Control
Holding
Set
Bit 5
Parity
Enable
Register
Ready
(AUTO)
(THRE)
(DSR)
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled‡
Receiver
Trigger
(LSB)
Break
Control
Transmitter
Ring
0
Empty
Indicator
Bit 6
(TEMT)
(RI)
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
Divisor
0
FIFOs
Enabled‡
Receiver
Trigger
(MSB)
Latch
Access
Bit
0
(DLAB)
Error in
Receiver
FIFO
(see
Note 6)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
† _{Bit 0 is the least significant bit. It is the first bit serially transmitted or received.}
‡ _{These bits are always 0 in the TL16C450 mode.}
§ _{By setting this bit high in PNPBYPASS mode, the selected interrupt (IRQx) is enabled, otherwise, IRQx output is in the high-impedance state.}
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