TL16PNP550A Datasheet, PDF (26/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
READ op code transfer (see Figure 18)
Initially, the EEPROM chip select signal, S, which is connected to the TL16PNP550A EEPROM chip select (CS),
is raised. The EEPROM data, D/Q then samples the TL16PNP550A (SIO) line on the following rising edges of
the TL16PNP550A clock (SCLK), until a 1 is sampled and decoded by the EEPROM as a start bit. The
TL16PNP550A (SCLK) signal is connected to the EEPROM clock, C. The READ op code (10) is then sampled
on the next two rising edges of SCLK. TL16PNP550A sources the op code at the falling edges of SCLK.
C
(SCLK)
S
(CS)
D/Q
(SIO)
tw(SCLKH)
td1
td2
tw(SCLKL)
Start
Op Code Input = 1
tpd1
Op Code Input = 0
Start
Op Code Input
NOTE A: The corresponding TL16PNP550A terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together with a 2-kΩ resistor.
Figure 18. READ Op Code Transfer Waveforms
READ address and data transfer (see Figure 19)
After receiving the READ op code, the EEPROM samples the READ address on the next eight rising edges of
(SCLK). The device sources the address at the falling edge of SCLK. The EEPROM then sends out a dummy
0 bit on the D/Q line, which is followed by the 16-bit data word with the MSB first. Output data changes are
triggered by the rising edges of SCLK. The data is also read by the TL16PNP550A on the rising edges of SCLK.
C
(SCLK)
S
(CS)
D/Q
(SIO)
td2
tpd1
tpd2
tpd3
td3
Address Input
Data Output
NOTE A: The corresponding terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs are tied together
with a 2-kΩ resistor.
Figure 19. READ Address and Data Transfer Waveforms
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