TL16PNP550A Datasheet, PDF (22/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
PnP logical device control registers
The following registers are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus (see Table 6).
Table 6. PnP Logical Device Control Registers
ADDRESS PORT
VALUE
0×30
0×31
REGISTER NAME VALUE
READ/WRITE
CAPABILITY
POWER UP
ACTIVE
Read/write
00 00 00 00
This register controls whether the logical device is active on the bus.
Bit<7:1> Reserved and must be cleared.
Bit<0> When set, activates the logical device.
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, I/O range
check must be disabled.
I/O RANGE CHECK
Read/write
00 00 00 00
This register performs a conflict check on the I/O port range programmed for use by the logical device.
Bit<7:2> Reserved and must be cleared.
Bit<1> When set, I/O range check is enabled. I/O range check is only valid, when the logical device is
inactive.
Bit<0> When set, the logical device (an ACE in this case) responds to I/O reads of the logical device
(ACE) assigned I/O range with a 0×55 when I/O range check is in operation. When clear, the
logical device responds with a 0 × AA. This register is read/write.
PnP logical device configuration registers
These registers program the device ISA bus resource use (see Table 7).
Table 7. PnP Logical Device Configuration Registers
ADDRESS PORT
VALUE
0×60
0×61
0×70
0×71
0×74
0×75
REGISTER NAME VALUE
READ/WRITE
CAPABILITY
POWER UP
I/O PORT BASE ADDRESS [15:8]
Read/write
00
This register indicates the selected I/O upper limit address bits [15:8] for I/O descriptor 0. When the device is
activated, if there is an address match to register 0 × 61 and an address match to this register, a chip select is
generated.
Bit<7:2> Bits 15 – 10 are not supported, since the logical device uses 10-bit address decoding.
Bit<1:0> Indicates address bits 9 and 8.
I/O PORT BASE ADDRESS [7:0]
Read/write
00 00 00 00
This register indicates the selected I/O lower limit address bits [7:0] for I/O descriptor 0. When the device is activated,
if there is an address match to register 0 × 60 and an address match to this register, a chip select is generated.
Bit<2:0> Are not supported since the logical device has eight registers.
Bit<7:3> Indicates address bits 7 – 3.
INTERRUPT REQUEST LEVEL SELECT
Read/write
00 00
This register indicates the selected interrupt level.
Bit<3:0> Select the interrupt level. This device uses 10 interrupts from IRQ2 to IRQ7 and IRQ9 to IRQ12.
INTERRUPT REQUEST TYPE
Read
00 00 00 11
This register indicates which type of interrupt is used for the selected interrupt level.
Bit<7:2> Are reserved.
Bit<1> Is set to indicate active high.
Bit<0> Is set to indicate level sensitive.
DMA CHANNEL SELECT 0
Read only
00 00 01 00
This register has a value of 4 to indicate that DMA is not supported.
DMA CHANNEL SELECT 1
Read only
00 00 01 00
This register has a value of 4 to indicate that DMA is not supported.
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