TL16PNP550A Datasheet, PDF (30/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO time-out interrupt occurs as follows:
1. FIFO time-out interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received is longer than the four previous continuous character
times (if two stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO is longer than four previous continuous character
times. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.
2. Character times are calculated by using the internal receiver clock (RCLK) input for a clock signal (makes
the delay proportional to the baud rate). The RCLK frequency equals the clock frequency generated by the
prescalar block divided by the user-defined internal UART baud rate generator divisor.
3. When a time-out interrupt has occurred, it is cleared and the timer is reset when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:
1. The transmitter holding register empty interrupt [IIR (3–0) = 2] occurs when the transmit FIFO is empty. It
is cleared [IIR (3–0) = 1] as soon as the THR is written to (1 to 16 characters may be written to the transmit
FIFO while servicing this interrupt) or the IIR is read.
2. The transmitter FIFO empty indicator [LSR5 (THRE) = 1] is delayed one character time minus the last stop
bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last
time that THRE = 1. The first transmitter interrupt after changing FCR0 is immediate when it is enabled.
Character time-out and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
FIFO polled mode operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four puts the
ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately, either
one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR.
• LSR0 is set as long as there is one byte in the receiver FIFO.
• LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the transmit FIFO is empty.
• LSR6 indicates that both the transmit FIFO and shift registers are empty.
• LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmit FIFOs are still fully capable of holding characters.
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