TL16PNP550A Datasheet, PDF (10/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B – MARCH 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VOH‡
VOL‡
VOH
VOL
Il
IOZ
PARAMETER
High-level output voltage
Low-level output voltage
High-level output voltage
Low-level output voltage
Input current
High-impedance-state output cur-
rent
TEST CONDITIONS
IOH = – 12 mA
IOL = 24 mA
IOH = – 4 mA (see Note 2),
VCC = 0.8 V
IOL = 4 mA (see Note 2)
VCC = 5.25 V, VSS = 0,
VI = 0 to 5.25 V, All other terminals floating
VCC = 5.25 V, VSS = 0,
VO = 0 to 5.25 V,
Pullup and pulldown circuits are off
MIN
VCC– 0.8
VCC– 0.8
TYP†
MAX
0.5
0.5
±1
± 10
UNIT
V
V
V
V
µA
µA
ICC
Supply current
VCC = 5.25 V, TA = 25°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V,
Clock at 4 MHz (no crystal used),
No load on outputs,
Baud rate = 50 kbit/s
Ci(CLK)
Co(CLK)
Ci
Clock input capacitance
Clock output capacitance
Input capacitance
VCC = 0,
VSS = 0,
f = 1 MHz,
TA = 25°C,
All other terminals grounded
Co
Output capacitance
f(XIN–XOUT) Oscillator speed (XIN and XOUT)
† _{All typical values are at VCC = 5 V and TA = 25°C.}
‡ _{These parameters apply only for IRQx and D7 – D0.}
NOTE 2: These parameters apply for all outputs except XOUT, IRQx, and D7 – D0.
5 mA
15
20 pF
20
30 pF
6
10 pF
10
20 pF
16
22 MHz
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALTERNATE
SYMBOLS
TEST
CONDITIONS
MIN MAX UNIT
td1
Delay time, chip select (CS) high to clock (SCLK) high
tSHCH
td2
Input valid to clock (SCLK) high
tDVCH
tpd1
Propagation delay time, clock (SCLK) high to input transition
(SIO)
tCHDX
50
ns
100
ns
100
ns
tpd2
Propagation delay time, clock (SCLK) high to output valid
(SIO)
tCHQV
500 ns
tpd3
Propagation delay time, clock (SCLK) low to chip select
transition (CS)
tCLSL
See Figure 18
and Figure 19
2
clock
periods
td3
Delay time, chip select (CS) low to output Hi-Z (SIO)
tw(SCLKH)
Pulse duration, clock (SCLK) high to clock (SCLK) low
(see Note 3)
tSLQZ
tCHCL
100 ns
250
ns
tw(SCLKL)
Pulse duration, clock (SCLK) low to clock (SCLK) high
(see Note 3)
tCLCH
250
ns
fclock
Clock frequency (SCLK) (see Note 4)
FCLK
0.5 0.68 MHz
NOTES: 3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles according
to the ST93C56 specification.
4. The SCLK signal is attained by internally frequency dividing the XIN signal by 32.
10
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265