TMS320C6674_15 Datasheet, PDF (34/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6674
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS692E—March 2014
2.5.3.4 PCIe Boot Parameter Table
Table 2-19 PCIe Boot Mode Parameter Table
Byte
Offset
12
Name
Options
14
Address Width
16
Link Rate
18
Reference clock
20
Window 1 Size
22
Window 2 Size
24
Window 3 Size
26
Window 4 Size
28
Vendor ID
30
Device ID
32
Class code Rev ID MSW
34
Class code Rev ID LSW
36
SerDes Cfg MSW
38
SerDes Cfg LSW
40
SerDes lane 0 Cfg MSW
42
SerDes lane 0 Cfg LSW
44
SerDes lane 1 Cfg MSW
46
SerDes lane 1 Cfg LSW
End of Table 2-19
Description
Configured Through Boot
Configuration Pins
Bit 0 Mode
-
0 = Host mode (direct boot mode)
1 = Boot table boot mode
Bit 1 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bits 3-2 Reserved
Bit 4 Multiplier
0 = SerDes PLL configuration is done based on SerDes register values
1 = SerDes PLL configuration based on the reference clock values
Bits 15-5 Reserved
PCI address width, can be 32 or 64
-
SerDes frequency, in Mbps. Can be 2500 or 5000
-
Reference clock frequency, in units of 10 kHz. Value values are 10000
-
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz), and 31250
(312.5 MHz). A value of 0 means that value is already in the SerDes
configuration parameters and will not be computed by the boot ROM.
Window 1 size.
YES
Window 2 size.
YES
Window 3 size. Valid only if address width is 32.
YES
Window 4 Size. Valid only if the address width is 32.
YES
Vendor ID
-
Device ID
-
Class code revision ID MSW
-
Class code revision ID LSW
-
PCIe SerDes config word, MSW
-
PCIe SerDes config word, LSW
-
SerDes lane config word, MSW, lane 0
-
SerDes lane config word, LSW, lane 0
-
SerDes lane config word, MSW, lane 1
-
SerDes lane config word, LSW, lane 1
-
2.5.3.5 I²C Boot Parameter Table
Table 2-20 I²C Boot Mode Parameter Table (Part 1 of 2)
Byte Offset Name
12
Option
14
Boot Dev Addr
16
Boot Dev Addr Ext
Description
Bits 1-0 Mode
00b = Boot Parameter Table Mode
01b = Boot Table Mode
10b = Boot Config Mode
11b = Slave Receive Boot Config
Bits 15-2 Reserved
The I²C device address to boot from
Extended boot device address
Configured Through Boot
Configuration Pins
YES
YES
YES
34 Device Overview
Copyright 2014 Texas Instruments Incorporated
Submit Documentation Feedback