TMS320C6674_15 Datasheet, PDF (205/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6674
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS692E—March 2014
7.14 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
C6674 is supported only in master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
The C6674 SPI supports two modes, 3-pin and 4-pin. For the 4-pin chip-select mode, the C6674 supports up to two
chip selects.
7.14.1 SPI Electrical Data/Timing
7.14.1.1 SPI Timing
Table 7-67 SPI Timing Requirements
See Figure 7-42)
No.
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7 tsu(SDI-SPC) Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
7 tsu(SDI-SPC) Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
7 tsu(SDI-SPC) Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
7 tsu(SDI-SPC) Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
8 th(SPC-SDI) Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
8 th(SPC-SDI)
8 th(SPC-SDI)
8 th(SPC-SDI)
End of Table 7-67
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
Min
2
2
2
2
5
5
5
5
Max Unit
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-68 SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-42 and Figure 7-43)
No.
1 tc(SPC)
2 tw(SPCH)
3 tw(SPCL)
4 td(SDO-SPC)
4 td(SDO-SPC)
4 td(SDO-SPC)
4 td(SDO-SPC)
5 td(SPC-SDO)
5 td(SPC-SDO)
5 td(SPC-SDO)
5 td(SPC-SDO)
Parameter
Min
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
Cycle Time, SPICLK, All Master Modes
3*P2 ⁽¹⁾
Pulse Width High, SPICLK, All Master Modes
0.5*tc - 1
Pulse Width Low, SPICLK, All Master Modes
0.5*tc - 1
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 0.
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 1.
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 0
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 0 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 0 Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 1
Max
5
5
5
5
2
2
2
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 205