TMS320C6674_15 Datasheet, PDF (217/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6674
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS692E—March 2014
Table 7-76 EMIF16 Asynchronous Memory Timing Requirements ^{(1) (2)}
(see Figure 7-53 and Figure 7-54)
No.
24 t_w(WEL)
24 t_w(WEL)
26 t_osu(DV-WEL)
27 t_oh(WEH-DIV)
25 t_d(WAITH-WEH)
End of Table 7-76
WE active time low, when ew = 0. Extended wait mode is disabled.
WE active time low, when ew = 1. Extended wait mode is enabled.
Output setup time from D valid to WE low
Output hold time from WE high to D invalid
Delay time from WAIT deasserted to WE# high
Min
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
1 E = 1/SYSCLK7, RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold.
2 WAIT = number of cycles wait is asserted between the programmed end of the strobe period and wait de-assertion.
Max
Unit
ns
ns
ns
ns
4E + 3 ns
Figure 7-53 EMIF16 Asynchronous Memory Read Timing Diagram
3
EMIFCE[3:0]
EMIFR/W
EMIFBE[1:0]
EMIFA[21:0]
4
6
8
EMIFOE
EMIFD[15:0]
10
12
EMIFWE
Figure 7-54 EMIF16 Asynchronous Memory Write Timing Diagram
15
EMIFCE[3:0]
EMIFR/W
EMIFBE[1:0]
EMIFA[21:0]
16
18
20
22
24
EMIFWE
26
EMIFD[15:0]
EMIFOE
9
7
5
13
19
21
23
17
27
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Peripheral Information and Electrical Specifications 217