TMS320C6674_15 Datasheet, PDF (154/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6674
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS692E—March 2014
Table 7-30 PASS PLL Control Register 0 Field Descriptions
Bit
Field
31-24 BWADJ[7:0]
23
BYPASS
22-19 Reserved
18-6 PLLM
5-0
PLLD
End of Table 7-30
Description
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
Reserved
A 13-bit bus that selects the values for the multiplication factor
A 6-bit bus that selects the values for the reference divider
Figure 7-29 PASS PLL Control Register 1 (PASSPLLCTL1)
31
15
14
13
12
7
6
5
4
3
0
Reserved
PLLRST PLLSELECT
RW-00000000000000000
RW-0 RW-0
Legend: RW = Read/Write; -n = value after reset
Reserved
RW-000000
ENSAT
RW-0
Reserved
R-0
BWADJ[11:8]
RW-0000
Table 7-31 PASS PLL Control Register 1 Field Descriptions
Bit
31-15
14
Field
Reserved
PLLRST
13
PLLSELECT
12-7 Reserved
6
ENSAT
5-4 Reserved
3-0 BWADJ[11:8]
End of Table 7-31
Description
Reserved
PLL reset bit.
0 = PLL reset is released
1 = PLL reset is asserted
PASS PLL select bit. Note that this bit must be set before the Ethernet subsystem is configured and used.
0 = Reserved
1 = PASS PLL output clock is used as the input to PASS
Reserved
Must be set to 1 for proper operation of the PLL
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1
7.8.2 PASS PLL Device-Specific Information
As shown in Figure 7-27, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Network
Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS
PLL are affected as described in Section 7.5 ‘‘Reset Controller’’ on page 130. The PASS PLL is unlocked only during
the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of
the other resets.
7.8.3 PASS PLL Initialization Sequence
See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 72 for details on the initialization sequence for PASS PLL.
154 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
Submit Documentation Feedback