TLC5949 Datasheet, PDF (34/51 Pages) Texas Instruments – 16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp

TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
STATUS INFORMATION DATA (SID)
The status information data (SID) contain the status of the LED open detection (LOD), LED short detection
(LSD), output leakage detection (OLD), pre-thermal warning (PTW), thermal error flag (TEF), and IREF short flag
(ISF). When the LAT rising edge for a GS data write is input, the SID overwrite the common shift register data
after the data in the common shift register are copied to the GS latch. If the common shift register MSB is '1', the
SID data are not copied to the common shift register.
After being copied into the common shift register, new SID data cannot be copied until at least one new bit of
data is written into the common shift register. Otherwise, the LAT signal is ignored. To recheck SID without
changing the GS data, reprogram the common shift register with the same data currently programmed into the
GS latch. When LAT goes high, the GS data do not change, but the SID data are loaded into the common shift
register. LOD, LSD, OLD, PTW, TEF, and ISF are shifted out of SOUT with each SCLK rising edge. The SID
load configuration and SID read timing are shown in Figure 30 and Table 14, respectively.
Reserved
H[3:0]
LOD
Data
OUT[15:8]
Reserved
G[3:0]
LOD
Data
OUT[7:0]
Reserved
F[3:0]
LSD
Data
OUT[15:8]
Reserved
E[3:0]
LSD
Data
OUT[7:0]
Reserved
D[3:0]
OLD
Data
OUT[15:8]
Reserved
C[3:0]
OLD
Data
OUT[7:0]
Reserved
B[3:0]
TEF
PTW
ISF
Reserved
A[112:0]
SOUT
MSB
LSB
Common Common Common Common Common Common Common Common Common Common Common Common Common Common Common Common
Data Bit Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits Data Bits
192 [191:188] [187:180] [179:176] [175:168] [167:164] [163:156] [155:152] [151:144] [143:140] [139:132] [131:128] [127:120] [119:116] [115:113] [112:0]
SID are loaded to the
common shift register
at the LAT rising edge
when the common
shift register MSB is ‘0’.
SIN
SCLK
Common Shift Register (193 Bits)
Figure 30. SID Load Configuration
Table 14. SID Load Description
COMMON SHIFT
REGISTER BIT NUMBER
LOADED SID DESCRIPTION
Bits[112:0]
Reserved data. These 113 bits of data are not set and can be '0' or '1'.
Bit 113
IREF short flag (ISF) data; 1-bit data.
0 = Normal operation (default)
1 = IREF terminal connected to GND with low resistance
Bit 114
Pre-thermal warning (PTW) data; 1-bit data.
0 = Normal operation (default)
1 = Higher temperature condition than the detected PTW temperature range
Bit 115
Thermal error flag (TEF) data; 1-bit data.
0 = Normal operation (default)
1 = Higher temperature condition than the detected TEF temperature range
Bits[119:116]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
Output leakage detection (OLD) data bit for OUT0 to OUT7. The 8-bit data bit assignment of the output channel
is:
Bits[127:120]
Bit 120 = OUT0 OLD
Bit 121 = OUT1 OLD
…
Bit 126 = OUT6 OLD
Bit 127 = OUT7 OLD
0 = Normal operation (default)
1 = LED current leaks to GND when the output is off
Bits[131:128]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
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