TLC5949 Datasheet, PDF (28/51 Pages) Texas Instruments – 16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp

TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
193-Bit Common Shift Register
The 193-bit common shift register is used to shift data from the SIN pin into the TLC5949. The data shifted into
the register are used for GS and global BC functions. The common shift register LSB is connected to SIN and
the MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 193
bits are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered
up, the data in the 193-bit common shift register are random.
First and Second Grayscale (GS) Data Latch
The first and second GS data latches are each 192 bits long, and set the PWM timing for each constant-current
output. The on-time of all constant-current outputs is controlled by the data in the second GS data latch. A LAT
rising edge when the common shift register MSB is '0' shifts the least significant 192 bits of the common shift
register into the first GS latch. The GS data from the first latch are copied into the second latch either when the
4096th GSCLK occurs with the auto display repeat mode enabled, a LAT rising edge for a GS data write occurs
with the display timing reset mode enabled, or the BLANK bit in the first control data latch is set to '1'.
When the device is powered up, the data in the first and second latches are random. Therefore, GS data must
be written to the GS data latches before turning on the constant-current output. The first and second GS data
latch configurations are shown in Figure 28. The data bit assignment is shown in Table 5.
From Common Shift Register
First Grayscale (GS) Data Latch (192 Bits)
192 Bits
MSB
191
180
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is ‘0’.
Second Grayscale (GS) Data Latch (192 Bits)
192 Bits
MSB
191
180
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to ‘1’.
192 Bits
To GS Timing Control Circuit
Figure 28. First and Second Grayscale Data Latch Configuration
GS DATA LATCH BIT
NUMBER
11-0
23-12
35-24
47-36
59-48
71-60
83-72
95-84
Table 5. Grayscale Data Latch Bit Description
BIT NAME
GSOUT0
GSOUT1
GSOUT2
GSOUT3
GSOUT4
GSOUT5
GSOUT6
GSOUT7
CONTROLLED
CHANNEL
Bits 11 to 0 for OUT0
Bits 11 to 0 for OUT1
Bits 11 to 0 for OUT2
Bits 11 to 0 for OUT3
Bits 11 to 0 for OUT4
Bits 11 to 0 for OUT5
Bits 11 to 0 for OUT6
Bits 11 to 0 for OUT7
GS DATA LATCH BIT
NUMBER
107-96
119-108
131-120
143-132
155-144
167-156
179-168
191-180
BIT NAME
GSOUT8
GSOUT9
GSOUT10
GSOUT11
GSOUT12
GSOUT13
GSOUT14
GSOUT15
CONTROLLED
CHANNEL
Bits 11 to 0 for OUT8
Bits 11 to 0 for OUT9
Bits 11 to 0 for OUT10
Bits 11 to 0 for OUT11
Bits 11 to 0 for OUT12
Bits 11 to 0 for OUT13
Bits 11 to 0 for OUT14
Bits 11 to 0 for OUT15
28
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