TLC5949 Datasheet, PDF (31/51 Pages) Texas Instruments – 16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp

TLC5949
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BIT
NUMBER
129
130
131, 132
133
134-136
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
Table 7. Function Control Data Latch Bit Description (continued)
BIT
NAME
IDMENA
IDMRPT
IDMCUR
OLDENA
PSMODE
DEFAULT
VALUE
(Binary)
—
—
—
—
111
DESCRIPTION
Invisible detection mode (IDM) enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', IDM is disabled. Therefore, LOD and LSD check LED status
only at power-up.
When this bit is '1', LOD and LSD check LED status with very small current
sinking at OUTn in a specific display segment. LOD and LSD can be checked
even if OUTn is off. The current value is set by the IDMCUR bits (bits 132, 131)
and the time is set by the LATTMG bits (bits 128, 127) in the function control
data latch. Furthermore, the IDM operation is repeated every display period
with auto display mode enabled when the IDMRPT bit (bit 130) is set to '1'.
When the device is powered on, this bit is random.
Invisible detection mode (IDM) repeat bit
0 = Not repeated, 1 = Repeated
When this bit is '0', IDM is not repeated. Therefore, LOD and LSD check LED
status only one time after the BLANK bit is changed from '1' to '0'. Otherwise,
LAT is input for a GS write when TMGRST is '1' or the GS counter is reset at
power-up only one time at the time programmed by LATTMG. IDM is disabled
when IDMENA is set to '0' even if this bit is '1'.
When this bit is '1', IDM operation is repeated every display period with the auto
display mode enabled. LOD and LSD check LED status at OUTn every display
period even if OUTn is off. When the device is powered on, this bit is random.
Invisible detection mode (IDM) current select bits
The OUTn sink current for IDM can be selected with these bits. Refer to
Table 11 for the IDM sink current truth table. When the device is powered on,
these bits are random.
Output leak detection mode (OLD) enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', OLD is not checked and all OLD bits in the status
information data (SID) are set to '0'. OLD data are loaded into the OLD data
latch at the 4095th GS clock. OLD data in SID may show the result of the
previous display period, depending on the LAT input timing.
When this bit is '1', OLD checks the LED status with a small current sourced
through OUTn in a display segment. OLD only checks OUTn with GS data set
to '0'. When OUTn current leakage is detected, the OLD bit that corresponds to
the leaking output is set to '1' in the SID. When IDMENA is '1', OLD operation is
disabled even if the OLDENA bit is set to '1' because OLD cannot obtain a
correct result when IDM is enabled. When the device is powered on, this bit is
random.
Power-save mode (PSM) selection bits
The power-save mode is selected with these bits. Refer to Table 12 and
Table 13 for the PSM truth tables. When the device is powered on, these bits
are all set to '1'.
Copyright © 2012, Texas Instruments Incorporated
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