TLC5949 Datasheet, PDF (27/51 Pages) Texas Instruments – 16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp

TLC5949
www.ti.com
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
REGISTER AND DATA LATCH CONFIGURATION
The TLC5949 has one common shift register and two pairs of data latches: the first and second grayscale (GS)
data latches and the first and second control data latches. The common shift register is 193 bits long and the GS
data latches are 192 bits long in total. The first control data latch is 137 bits long and the second latch is 119 bits
long. When the common shift register MSB is '0', the least significant 256 bits from the common shift register are
latched into the first GS data latch. When the MSB is '1', the data are latched into the first control data latch.
Figure 27 shows the common shift register and latch configurations.
Common Shift Register (193Bits)
SOUT
MSB
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Bit
191
190
189
188
187
192
191
190
189
188
187
LSB
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
5
4
3
2
1
0
5
4
3
2
1
0
SIN
SCLK
Lower 192 Bits
First Grayscale (GS) Data Latch (192 Bits)
192 Bits
MSB
191
180
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is '0'.
Second Grayscale (GS) Data Latch (192 Bits)
192 Bits
MSB
191
180
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
192 Bits
To GS Timing Control Circuit
First Control Data Latch (137 Bits)
Lower 137 Bits of 192 Bits
MSB
136-119 118-112 111-105 104-98
FUNC BC
Bits Bits[6:0]
17-0 ^{for OUTn}
(1)
RSV
Bits
RSV
Bits
FC,
BC,
18 Bits 7 Bits
97-91 90-84
RSV
Bits
RSV
Bits
27-21 20-14
RSV
Bits
RSV
Bits
112 Reserved Bits (Write ‘1’ to All Bits)
13-7
RSV
Bits
LSB
6-0
RSV
Bits
Second Control Data Latch (119 Bits)
119 Bits
18 Bits
MSB
118-112 111-105 104-98
BC
Bits[6:0]
for OUTn
RSV
Bits
RSV
Bits
BC,
7 Bits
7 Bits
97-91 90-84
RSV
Bits
RSV
Bits
27-21 20-14
RSV
Bits
RSV
Bits
112 Reserved Bits (Write '1' to All Bits)
112 Bits
13-7
RSV
Bits
LSB
6-0
RSV
Bits
This latch pulse
comes from the
LAT pin when the
MSB of the Common
Shift Register is ‘1’.
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
To
To
Function Global Brightness
Control Circuit Control Circuit
(1) RSV = reserved.
No
Applied
Bits
Figure 27. Common Shift Register and Control Data Latches Configuration
Copyright © 2012, Texas Instruments Incorporated
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