TLC5949 Datasheet, PDF (24/51 Pages) Texas Instruments – 16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp

TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 24. This
function is switched on or off by the content of the DSPRPT bit in the first control data latch.
When the DSPRPT bit is '1', auto display repeat is enabled and the entire display period automatically repeats.
When the DSPRST bit is '0', the auto display repeat is disabled and the entire display period executes only one
time after either the BLANK bit is changed from '1' to '0', or after a LAT signal rising edge for a GS data write is
input when the display timing reset is enabled.
BLANK Bit
in First Control Data Latch
(Internal)
GSCLK
DSPRPT Bit
in First Control Data Latch
(Internal)
BLANK = 1 (Blank)
12345
BLANK = 0 (Not Blank)
4094
1
4
4095
2
5
4093 4096
3
4094
1
4095
4095
2
4093 4096
3 4 5 6 7 8 9 10
'1' (Auto Display
Repeat Enabled)
1st Entire Display Period
2nd Entire Display Period
3rd Entire Display Period
12
4094
1
4095
2
4096
DSPRPT = 0
(Auto Display
Repeat Disabled)
1st Entire
Display Period
OUTn
(GS Data = FFFh)
OFF
ON
Display period is repeated with
Auto display repeat function.
OUTn is forced off
when BLANK is set to '1'.
Note (1)
(1) OUTn is not turned on until BLANK changes from '1' to '0' or until LAT changes from low to high for a GS data write with TMGRST = 1.
Figure 24. Auto Display Repeat Function
Auto Data Refresh Function
This function allows grayscale (GS) data and global brightness control (BC) data to be input at any time without
synchronizing the input to the display timing. If GS and BC data are sent during a display period, the input data
are held in the first latch for each data register. The data are then transferred to the second latch when the
4096th GSCLK occurs. The second latch data are used for the next display period. Refer to Figure 25 and
Figure 26 for the auto data refresh function timing. However, when the BLANK bit in the first control data latch is
set to '1' before the 4096th GSCLK occurs, the first latch data immediately upload to the second latch. Also,
when a LAT rising edge occurs while the BLANK bit is '1', the selected shift register data are transferred to the
first and second latch at the same time. The data of bits 119-136 (BLANK, DSPRPT, TMGRST, ESPWM,
LODVLT, LSDVLT, LATTMG, IDMENA, IDMRPT, IDMCUR, OLDEN, and PSMODE) in the control data latch
immediately update whenever the data are written into the first latch.
24
Submit Documentation Feedback
Product Folder Links: TLC5949
Copyright © 2012, Texas Instruments Incorporated