DS110RT410 Datasheet, PDF (34/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460 – MAY 2013
www.ti.com
merit starts to degrade, the DS110RT410 still continues to try additional CTLE settings for a pre-determined trial
count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE
boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in
register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by
default.
The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers
0x40-0x5f. The default values for these settings are shown in Table 14. These values may be overridden by
setting the corresponding register values over the SMBus. If these values are overridden, then the next time the
CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the
adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost
settings to their defaults. So will power-cycling the DS110RT410.
Register (Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
Bits 7:6 (CTLE
Stage 0)
0
0
0
0
1
0
0
2
0
0
0
1
1
3
1
2
2
2
2
1
1
2
2
3
1
1
1
1
3
2
2
2
Table 14. CTLE Settings for Adaptation
Bits 5:4 (CTLE
Stage 1)
0
0
0
1
0
0
0
0
0
0
3
0
1
0
2
1
0
0
2
0
1
0
3
0
1
1
2
3
1
1
1
2
Bits 3:2 (CTLE
Stage 2)
0
0
1
0
0
2
0
0
0
3
0
0
0
0
0
0
2
0
0
1
0
3
0
2
1
3
2
1
1
2
1
1
Bits 1:0 (CTLE
Stage 3)
0
1
0
0
0
0
2
0
3
0
0
1
0
0
0
0
0
2
0
2
2
0
0
0
3
1
1
1
1
1
2
1
CTLE Boost
String
0000
0001
0010
0100
1000
0020
0002
2000
0003
0030
0300
1001
1100
3000
1200
2100
2020
2002
2200
1012
1102
2030
2300
3020
1113
1131
1221
1311
3111
2121
2112
2211
CTLE Adaptation
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
34
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