DS110RT410 Datasheet, PDF (11/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
www.ti.com
DEVICE CONFIGURATION INFORMATION
SNLS460 – MAY 2013
The DS110RT410 can be configured by the user to optimize its operation. The four channels can be optimized
independently in SMBus master or SMBus slave mode. The operational settings available for user configuration
include the following.
• CTLE boost setting
• Data Rate and Standard Setting
• Reference clock setting
• Driver output voltage
• Driver output de-emphasis
• Driver output rise/fall time
Configuration of the DS110RT410 is accomplished by writing the appropriate values into various device registers
over the SMBus. This can either be done while the device is operating or upon initial power-up. When the
DS110RT410 is operating it behaves like an SMBus slave device, and its register contents can be read or written
over the SMBus. Optionally, when the DS110RT410 first powers up, it can behave like an SMBus master and
read its register contents autonomously from an external EEPROM.
CTLE Boost Setting
The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The
overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of
the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage
generally increases with increasing boost settings.
The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal.
Automatic adaptation of the CTLE only is the default mode of operation for the DS110RT410.
Data Rate and Standard Setting
Register 0x2f, bits 7:4, Register 0x36, bits 2:0, and Registers 0x60, 0x61, 0x62, 0x63, and 0x64
The DS110RT410 is part of a family of retimer devices differentiated by different VCO frequency ranges. Each
device in the retimer family is designed for operation in specific frequency bands and with specific data rate
standards.
The DS110RT410 is designed to lock rapidly to any valid signal present at its inputs. It is also designed to detect
incorrect lock conditions which can arise when the input data signals are strongly periodic. This condition is
referred to as “false lock”. The DS110RT410 discriminates against false lock by using its 25 MHz reference to
ensure that the VCO frequency resulting from its internal phase-locking process is correct.
To determine the correct VCO frequency, the digital circuitry in the DS110RT410 requires some user-supplied
information about the expected data rate or data rates. This information is provided by writing several device
register using the SMBus.
Standards-Based Modes
The DS110RT410 is designed to automatically operate with various multi-band data standards.
The first set of register writes constrain the coarse VCO tuning and the VCO divider ratios. When these registers
are set as indicated in Table 1, the DS110RT410 restricts its coarse VCO tuning to a set of coarse tuning values.
It also restricts the VCO divider ratio to the set of divider ratios required to cover the frequency bands for the
desired data rate standard. This enables the DS110RT410 to acquire phase lock more quickly than would be
possible if the coarse tuning range were unrestricted.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DS110RT410
Submit Documentation Feedback
11