DS110RT410 Datasheet, PDF (23/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
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Address (Hex) Bits
0x09
7
5
2
0x0a
3
2
0x0b
4:0
0x0d
5
0x11
7:6
5
0x13
2
0x14
7
6
0x15
6
2:0
0x18
6:4
2
0x1e
7:5
4
0x1f
7
0x24
7
0
0x25
7:0
0x26
7:0
0x27
7:0
0x28
7:0
0x29
6:5
0x2a
7:0
0x2d
2:0
0x2f
7:6
5:4
3
2
1
0
0x30
4
3
1:0
0x31
6:5
4:3
0x32
7:4
3:0
0x33
7:4
3:0
SNLS460 – MAY 2013
Table 7. Channel Registers (continued)
Default Value (Hex)
0x0
0x0
0x0
0x0
0x0
0x0f
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x4
0x0
0x7
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x30
0x0
0x0
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x1
0x0
0x1
0x1
0x8
0x8
Mode Field Name
R/W reg_divsel_vco_cap_ov
R/W reg_bypass_pfd_ov
R/W reg_divsel_ov
R/W reg_cdr_reset_ov
R/W reg_cdr_reset_sm
R/W cdr_cap_dac_start1[4:0]
R/W PRBS_PATT_SHIFT_EN
R/W eom_sel_vrange[1:0]
R/W eom_PD
RW
eq_BST3[2]
R/W eq_sd_preset
R/W eq_sd_reset
R/W drv_dem_range
R/W drv_dem[2:0]
R/W pdiq_sel_div[2:0]
R/W drv_sel_slow
R/W pfd_sel_data_mux[2:0]
R/W prbs_en
R/W drv_sel_inv
R/W fast_eom
R/W/SC eom_start
R
eom_count[15:8]
R
eom_count[7:0]
R
heo[7:0]
R
veo[7:0]
R
eom_vrange_setting[1:0]
R/W eom_timer_thr[7:0]
R/W drv_sel_vod[2:0]
R/W RATE[1:0]
R/W SUBRATE[1:0]
R/W index_ov
R/W en_ppm_check
R/W en_fld_check
R/W ctle_adapt
R
heo_veo_interrupt
R/W prbs_en_dig_clk
R/W prbs_pattern_sel[1:0]
R/W adapt_mode[1:0]
R/W eq_sm_fom[1:0]
R/W heo_int_thresh[3:0]
R/W veo_int_thresh[3:0]
R/W heo_thresh[3:0]
R/W veo_thresh[3:0]
Description
Enable Override VCO Cap DAC (Registers 0x08
and 0x0b)
Enable Override Output Mux (Register 0x1e)
Enable Override Divider Select (Register 0x18)
Enable CDR Reset Override (Register 0x0a)
CDR Reset Override Bit
Override VCO Cap DAC Setting 1 <4:0>
PRBS Generator Clock Enable
Eye Opening Monitor Voltage Range <1:0>
Eye Opening Monitor Power Down
CTLE Boost Stage 3, Bit 2 (Limiting Bit)
Force Signal Detect On
Force Signal Detect Off
Driver De-emphasis Range
Driver De-emphasis Setting<2:0>
VCO Divider Ratio <2:0> (Enable from Register
0x09, Bit 2)
Enable Slow Rise/Fall Time on Output Driver
OutputMux <2:0> (Enable from Register 0x09, Bit
5)
Enable PRBS Generator
Select Output Polarity Inverted
Enable Fast Eye Opening Monitor Mode
Start Eye Opening Monitor Counter (Self-
Clearing)
Eye Opening Monitor Count <15:8>
Eye Opening Monitor Count <7:0>
HEO Value <7:0>
VEO Value <7:0>
Eye Opening Monitor Voltage Range Setting
<1:0>
Eye Opening Monitor Timer Threshold <7:0>
Driver VOD <2:0>
Rate <1:0> (see Table 1)
Subrate <1:0> (see Table 1)
CTLE Adaptation Index Override (Register 0x13)
Enable Frequency Counter for Lock Detect
False Lock Detector for lock detect is disabled by
default. Must set bit to 0 to enable the FLD.
Start CTLE Adaptation
Goes High if Interrupt from CDR Goes High
PRBS Generator Enable
PRBS Generator Pattern Select <1:0>
Adaptation Mode <1:0>
CTLE Adaptation Figure of Merit Type <1:0>
HEO Interrupt Threshold <3:0>
VEO Interrupt Threshold <3:0>
HEO Threshold for CTLE Adaptation Handoff
VEO Threshold for CTLE Adaptation Handoff
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