DS110RT410 Datasheet, PDF (24/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460 – MAY 2013
www.ti.com
Table 7. Channel Registers (continued)
Address (Hex)
0x36
0x39
0x3a
0x3e
0x40 – 0x5f
0x60
0x61
0x62
0x63
0x64
0x6a
0x6b
0x6c
0x6d
0x6e
0x70
Bits Default Value (Hex) Mode Field Name
Description
6
0x0
R/W heo_veo_int_enable
Enable HEO/VEO Interrupt
5:4
0x3
R/W ref_mode[1:0]
Reference Clock Mode <1:0>
2
0x0
R/W mr_cdr_cap_dac_rng_ov Enable Override for VCO Cap DAC Range
1:0
0x1
R/W mr_cdr_cap_dac_rng[1:0] Cap DAC Range <1:0>
4:0
0x0
R/W start_index[4:0]
Start Index for CTLE Adaptation <4:0> (Enable
from Register 0x2f, Bit 3)
7:6
0x2
R/W fixed_eq_BST0[1:0]
Fixed CTLE Stage 0 Boost Setting for Lower Data
Rates <1:0>
5:4
0x2
R/W fixed_eq_BST1[1:0]
Fixed CTLE Stage 1 Boost Setting for Lower Data
Rates <1:0>
3:2
0x1
R/W fixed_eq_BST2[1:0]
Fixed CTLE Stage 2 Boost Setting for Lower Data
Rates <1:0>
1:0
0x1
R/W fixed_eq_BST3[1:0]
Fixed CTLE Stage 3 Boost Setting for Lower Data
Rates <1:0>
7
0x1
R/W HEO_VEO_LOCKMON_E Enable HEO/VEO Lock Monitoring
N
CTLE Settings for Adaptation – see Table 14
7:0
0x00
R/W grp0_ov_cnt[7:0]
PPM count, Group 0, lower-order byte
7
0x0
R/W cnt_dlta_ov_0
Override PPM count and delta for Group 0
6:0
0x00
R/W grp0_ov_cnt[14:8]
PPM count, Group 0, higher-order byte
7:0
0x00
R/W grp1_ov_cnt[7:0]
PPM count, Group 1, lower-order byte
7
0x0
R/W cnt_dlta_ov_1
Override PPM count and delta for Group 1
6:0
0x00
R/W grp1_ov_cnt[14:8]
PPM count, Group 1, higher-order byte
7:4
0x0
R/W grp0_ov_dlta[3:0]
PPM count delta, Group 0
3:0
0x0
R/W grp1_ov_dlta[3:0]
PPM count delta, Group 1
7:4
0x4
R/W veo_lck_thrsh[3:0]
Vertical Eye Opening Lock Threshold <3:0>
3:0
0x4
R/W heo_lck_thrsh[3:0]
Horizontal Eye Opening Lock Threshold <3:0>
7:0
0x0
R/W fom_a[7:0]
Adaptation Figure of Merit Term a<7:0>
7:0
0x0
R/W fom_b[7:0]
Adaptation Figure of Merit Term b<7:0>
7:0
0x0
R/W fom_c[7:0]
Adaptation Figure of Merit Term c<7:0>
7
0x0
R/W en_new_fom_ctle
Enable Alternate Figure of Merit for CTLE
Adaptation
2:0
0x3
R/W eq_lb_cnt[2:0]
CTLE Adaptation Look-Beyond Count <2:0>
Resetting Individual Channels of the Retimer
Register 0x00, bit 2, and register 0x0a, bits 3:2
Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory
default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the
DS110RT410 since it was powered-up.
To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and
adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the
reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same
operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal
is present at the input to the selected channel, the DS110RT410 will attempt to lock to it and will adapt its CTLE.
Interrupt Status
Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and
Register 0x36, bit 6
24
Submit Documentation Feedback
Product Folder Links: DS110RT410
Copyright © 2013, Texas Instruments Incorporated