DS110RT410 Datasheet, PDF (26/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460 – MAY 2013
www.ti.com
To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE
boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the
table.
The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this
additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13.
If the DS110RT410 loses lock because of a change in the CTLE settings, the device will initiate its lock and
adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which cause the
device to drop out of lock, the DS110RT410 may in the process of reacquiring the CDR lock, reset the CTLE
settings to different values than those you set in register 0x03 and 0x13. If this behavior is not understood, it can
appear that the DS110RT410 did not accept the values you wrote to the CTLE boost registers. What's really
happening, however, is that the lock and adaptation sequence is overriding the CTLE values you wrote to the
CTLE boost registers. This will not happen unless the DS110RT410 drops out of lock.
If the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be
overridden, but the DS110RT410 may still lose lock. If this happens, the device will attempt to reacquire lock.
The DS110RT410 will begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the
lowest configured bit rate. At divider values of 4 and 8, the CTLE boost settings used will come not from the
values in register 0x03, and 0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data
rates. This setting will be written into boost setting register 0x03 during the lock search process. This value may
be different from the value you set in register 0x03, so, again, it may appear that the DS110RT410 has not
accepted the CTLE boost settings you set in registers 0x03 and 0x13. The interactions of the lock and adaptation
sequences with the manually-set CTLE boost settings can be difficult to understand.
To manually override the CTLE boost under all conditions, perform the following steps.
1. Set the DS110RT410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
2. Set the desired CTLE boost setting in register 0x3a. If the DS110RT410 loses lock and attempts to lock to a
lower data rate, it will use this CTLE boost setting.
3. Set the desired CTLE boost setting in register 0x03.
4. Set the desired CTLE boost setting in register 0x40.
5. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.
If the DS110RT410 loses lock when the CTLE boost settings are set according to the sequence above, the
DS110RT410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.
Overriding the VCO CAP DAC Values
Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4, and Register 0x2f,
bits 7:6 and 5:4
Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to
2'b11, then the DS110RT410 performs an initial search to determine the correct CAP DAC setting (coarse VCO
tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f)
determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference
for the frequency search.
The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1)
and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override
CAP DAC values to take effect. Since some rate and subrate setting combinations apply to multiple data rates,
there are two CAP DAC values for some rates. The first is in register 0x08, bits 4:0, and the second is in register
0x0b, bits 4:0. The DS110RT410 will use the CAP DAC value in register 0x08 for the larger divide ratios
associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the CAP
DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the selected rate
and subrate. it will continue to try to acquire lock in this way until it either succeeds or the override bit (bit 7 of
register 0x09) is cleared.
Overriding the Output Multiplexer
Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5
By default, the DS110RT410 output for each channel will be as shown in Table 8.
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