DS110RT410 Datasheet, PDF (21/40 Pages) Texas Instruments – DS110RT410 Low Power Multi-Rate Quad Channel Retimer

DS110RT410
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SNLS460 – MAY 2013
SMBus Master Mode Control Bits
Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4
Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the
DS110RT410 is in SMBus slave mode. This is an undefined condition.
When this bit is set, if the EN_SMB pin is floating (meaning that the DS110RT410 is in SMBus master mode),
then the DS110RT410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This
bit is not self-clearing, so it should be cleared after it is set.
When the DS110RT410 EN_SMB pin is floating (meaning that the device is in SMBus master mode), it will read
from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is complete,
register 0x05, bit 4 will be set. Alternatively, the DS110RT410 will read from its external EEPROM when triggered
by register 0x04, bit 4, as described below.
When register 0x04, bit 4, is set, the DS110RT410 reads its configuration from an external EEPROM over the
SMBus immediately. When this bit is set, the DS110RT410 does not wait until the READ_EN pin is pulled low to
read from the EEPROM. This EEPROM read occurs whether the DS110RT410 is in SMBus master mode or not.
If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the
DS110RT410 may hang up and a power-up reset may be necessary to return it to proper operation. You should
only set this bit if you know that the EEPROM is present and properly configured.
If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause
the DS110RT410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the
SMBus master mode. If the DS110RT410 is not in SMBus master mode, do not set this bit. After setting this bit,
it should be cleared before further SMBus operations.
After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN
pin low or by then setting register 0x04, bit 4.
Register 0x05, bit 7, disables SMBus master mode. This prevents the DS110RT410 from trying to take command
of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has
already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in
which disabling EEPROM master mode read is valid are (1) when the DS110RT410 is in SMBus master mode,
but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus
master mode but the EEPROM read operation has not yet occurred.
Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the
DS110RT410 to hang up.
Channel Select Register
Register 0xff, bits 3:0
Register 0xff, as described above, selects the channel or channels for channel register reads and writes. It is
worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel
register write applies to all channels. Channel register read operations always target only the channel specified in
bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the
channel register sets only when bit 2 of register 0xff is set.
Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register
reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for
example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In
order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the
control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target
the register with address 0xff in the control/shared register set. There is no other register, and specifically, no
channel register, with address 0xff.
The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations
on this register will always yield an invalid result. All eight bits of this register should always be set to the desired
values whenever this register is written. Always write 0x0 to the four MSBs of register 0xff. The register set target
selected by each valid value written to the channel select register is shown in Table 6
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