AM1808_1008 Datasheet, PDF (230/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
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Table 6-120. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see Figure 6-74)
NO.
1
t_{su(VDINV-VKIH)}
2
t_{h(VKIH-VDINV)}
PARAMETER
Setup time, VP_DINx valid before VP_CLKIN0/1 high
Hold time, VP_DINx valid after VP_CLKIN0/1 high
1.3V, 1.2V
MIN MAX
4
0
1.1V
MIN MAX
6
0
1.0V
MIN MAX
7
0
UNIT
ns
ns
VP_CLKIN0/1
1
2
VP_DINx/FIELD/
HSYNC/VSYNC
Figure 6-74. VPIF Channels 0/1 Video Capture Data and Control Input Timing
Table 6-121. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown
With Respect to VP_CLKOUT2/3⁽¹⁾
(see Figure 6-75)
NO.
1 t_c(VKO)
2 t_w(VKOH)
3 t_w(VKOL)
4 t_t(VKO)
11 t_{d(VKOH-VPDOUTV)}
12 t_{d(VCLKOH-VPDOUTIV)}
PARAMETER
Cycle time, VP_CLKOUT2/3
Pulse duration, VP_CLKOUT2/3 high
Pulse duration, VP_CLKOUT2/3 low
Transition time, VP_CLKOUT2/3
Delay time,
VP_CLKOUT2/3 high to VP_DOUTx valid
Delay time,
VP_CLKOUT2/3 high to VP_DOUTx invalid
1.3V, 1.2V
MIN MAX
13.3
0.4C
0.4C
5
1.1V
MIN MAX
20
0.4C
0.4C
5
1.0V
MIN MAX
37
0.4C
0.4C
5
UNIT
ns
ns
ns
ns
8.5
12
17 ns
1.5
1.5
1.5
ns
(1) C = VP_CLKO2/3 period in ns.
VP_CLKOUTx
(Positive Edge
Clocking)
4
VP_CLKOUTx
(Negative Edge
Clocking)
2
1
3
4
11
12
VP_DOUTx
Figure 6-75. VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3
230 Peripheral Information and Electrical Specifications
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