AM1808_1008 Datasheet, PDF (128/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
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6.14.2 1. SATA Interface
This section provides the timing specification for the SATA interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the SATA interface
requirements are met.
6.14.2.1 SATA Interface Schematic
Figure 6-28 shows the SATA interface schematic.
SATA Interface(Processor)
0.1uF
SATA_TXN
SATA_TXP
0.1uF
0.1uF
SATA_RXN
SATA_RXP
0.1uF
SATA_REFCLKN
SATA_REFCLKP
0.1uF
0.1uF
SATA Connector
TX–
TX+
RX–
RX+
LVDS
Oscillator
CLK–
CLK+
SATA_REG
0.1uF
Figure 6-28. SATA Interface High Level Schematic
6.14.2.2 Compatible SATA Components and Modes
Table 6-43 shows the compatible SATA components and supported modes. Note that the only supported
configuration is an internal cable from the processor host to the SATA device.
Table 6-43. SATA Supported Modes
PARAMETER
Transfer Rates
eSATA
xSATA
Backplane
Internal Cable
MIN MAX UNIT SUPPORTED
1.5 3.0 Gbps
No
No
No
Yes
6.14.2.3 PCB Stackup Specifications
Table 6-44 shows the stackup and feature sizes required for SATA.
Table 6-44. SATA PCB Stackup Specifications
PARAMETER
PCB Routing/Plane Layers
Signal Routing Layers
Number of ground plane cuts allowed within SATA routing region
MIN TYP MAX UNIT
4
6
Layers
2
3
Layers
0
Layers
128 Peripheral Information and Electrical Specifications
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