AM1808_1008 Datasheet, PDF (108/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
6.11.2 DDR2/mDDR Controller Register Description(s)
BYTE ADDRESS
0xB000 0000
0xB000 0004
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
0xB000 00E4
0x01E2 C000
Table 6-24. DDR2/mDDR Controller Registers
ACRONYM
REVID
SDRSTAT
SDCR
SDRCR
SDTIMR1
SDTIMR2
SDCR2
PBBPR
PC1
PC2
PCC
PCMRS
PCT
IRR
IMR
IMSR
IMCR
DRPYC1R
VTPIO_CTL
REGISTER DESCRIPTION
Revision ID Register
SDRAM Status Register
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration Register 2
Peripheral Bus Burst Priority Register
Performance Counter 1 Registers
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
Interrupt Mask Register
Interrupt Mask Set Register
Interrupt Mask Clear Register
DDR PHY Control Register 1
VTP IO Control Register
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6.11.3 DDR2/mDDR Interface
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2
Timing Specification (SPRAAV0).
6.11.3.1 DDR2/mDDR Interface Schematic
Figure 6-16 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The
dual-memory system shown in Figure 6-17. Pin numbers for the device can be obtained from the pin
description section.
108 Peripheral Information and Electrical Specifications
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