AM1808_1008 Datasheet, PDF (133/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
Table 6-49. McASP Registers Accessed Through Peripheral Configuration Port (continued)
BYTE ADDRESS
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 013C
0x01D0 0140
0x01D0 0144
0x01D0 0148
0x01D0 014C
0x01D0 0150
0x01D0 0154
0x01D0 0158
0x01D0 015C
0x01D0 0180
0x01D0 0184
0x01D0 0188
0x01D0 018C
0x01D0 0190
0x01D0 0194
0x01D0 0198
0x01D0 019C
0x01D0 01A0
0x01D0 01A4
0x01D0 01A8
0x01D0 01AC
0x01D0 01B0
0x01D0 01B4
0x01D0 01B8
0x01D0 01BC
0x01D0 0200
0x01D0 0204
0x01D0 0208
0x01D0 020C
0x01D0 0210
0x01D0 0214
0x01D0 0218
0x01D0 021C
ACRONYM
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
SRCTL0
SRCTL1
SRCTL2
SRCTL3
SRCTL4
SRCTL5
SRCTL6
SRCTL7
SRCTL8
SRCTL9
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
XBUF0 ⁽¹⁾
XBUF1 ⁽¹⁾
XBUF2 ⁽¹⁾
XBUF3 ⁽¹⁾
XBUF4 ⁽¹⁾
XBUF5 ⁽¹⁾
XBUF6 ⁽¹⁾
XBUF7 ⁽¹⁾
REGISTER DESCRIPTION
Left (even TDM time slot) channel status register (DIT mode) 2
Left (even TDM time slot) channel status register (DIT mode) 3
Left (even TDM time slot) channel status register (DIT mode) 4
Left (even TDM time slot) channel status register (DIT mode) 5
Right (odd TDM time slot) channel status register (DIT mode) 0
Right (odd TDM time slot) channel status register (DIT mode) 1
Right (odd TDM time slot) channel status register (DIT mode) 2
Right (odd TDM time slot) channel status register (DIT mode) 3
Right (odd TDM time slot) channel status register (DIT mode) 4
Right (odd TDM time slot) channel status register (DIT mode) 5
Left (even TDM time slot) channel user data register (DIT mode) 0
Left (even TDM time slot) channel user data register (DIT mode) 1
Left (even TDM time slot) channel user data register (DIT mode) 2
Left (even TDM time slot) channel user data register (DIT mode) 3
Left (even TDM time slot) channel user data register (DIT mode) 4
Left (even TDM time slot) channel user data register (DIT mode) 5
Right (odd TDM time slot) channel user data register (DIT mode) 0
Right (odd TDM time slot) channel user data register (DIT mode) 1
Right (odd TDM time slot) channel user data register (DIT mode) 2
Right (odd TDM time slot) channel user data register (DIT mode) 3
Right (odd TDM time slot) channel user data register (DIT mode) 4
Right (odd TDM time slot) channel user data register (DIT mode) 5
Serializer control register 0
Serializer control register 1
Serializer control register 2
Serializer control register 3
Serializer control register 4
Serializer control register 5
Serializer control register 6
Serializer control register 7
Serializer control register 8
Serializer control register 9
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Peripheral Information and Electrical Specifications 133
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