BQ26220 Datasheet, PDF (17/19 Pages) Texas Instruments – HIGH PERFORMANCE BATTERY MONITOR IC WITH COULOMB COUNTER, VOLTAGE AND TEMPERATURE MEASUREMENT

bq26220
SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
clear register (CLR)
The bits in the CLR register (address 0x63) clear the DCR, CCR, SCR, DTC, and CTC registers, reset the
bq26220 by forcing a power-on-reset and setting the state of the STAT pin as described in Table 11.
Table 11. CLR Register
7
(MSB)
RSVD
6
RSVD
5
RSVD
CLR BITS
4
3
CTC DTC
2
SCR
1
CCR
0
(LSB)
DCR
RSVD
CTC
DTC
SCR
CCR
DCR
Table 12. CLR Register Definitions
RSVD bits (bits 5, 6 and 7) are reserved for future use and should be written to 0 by the host.
CTC bit (bit 4) clears the CTCH and CTCL registers and the STC bit. A 1 clears the corresponding registers and
bit. After the registers are cleared, the CTC bit is cleared. This bit is cleared on power-on-reset.
DTC bit (bit 3) clears the DTCH and DTCL registers and the STD bit. A 1 clears the corresponding registers and
bit. After the registers are cleared, the DTC bit is cleared. This bit is cleared on power-on-reset.
SCR bit (bit 2) clears both the SCRH and SCRL registers. Writing a 1 to this bit clears the SCRH and SCRL
register. After these registers are cleared, the SCR bit is cleared. This bit is cleared on power-on-reset.
CCR bit (bit 1) clears both the CCRH and CCRL registers. Writing a 1 to this bit clears the CCRH and CCRL
registers. After these registers are cleared, the CCR bit is cleared. This bit is cleared on power-on-reset.
DCR bit (bit 0) clears both the DCRH and DCRL registers. Writing a 1 to this bit clears the DCRH and DCRL
registers. After these registers are cleared, the DCR bit is cleared. This bit is cleared on power-on-reset.
flash command register (FCMD)
The FCMD register (address 0x62) is the flash command register and programs a single flash byte-location,
perform flash page erase, transfer RAM to flash and flash to RAM, enter sleep mode, and power-down. These
functions are performed by writing the desired command code to the FCMD register. After the bq26220 has
finished executing the issued command, the flash command register is cleared.
0x0F
0x40
0x41
0x42
0x45
0x48
0xF6
Table 13. FCMD Register Definitions
Program byte command code. This code ANDs the contents of the FPD register with the contents of flash byte
location pointed to by the contents of the FPA register.
Erase page 0 command code. This code erases all the bytes of flash from address 0x00 to 0x1F.
Erase page 1 command code. This code erases all the bytes of flash from address 0x20 to 0x3F.
Erase page 2 command code. This code erases all the bytes of flash from address 0x40 to 0x5F.
RAM-to-flash transfer code. This code programs the contents of the RAM into Page 0 flash, addresses 0x00
though 0x1F.
Flash-to-RAM transfer code. This code copies the contents of the page 0 flash into RAM.
Power-down code. This code places the bq26220 into the sleep mode when the conditions are met as indicated
by the WOE bits in the MODE/WOE register. The part remains in sleep mode until a high-to-low or low-to-high
transition occurs on the HDQ pin.
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