BQ26220 Datasheet, PDF (16/19 Pages) Texas Instruments – HIGH PERFORMANCE BATTERY MONITOR IC WITH COULOMB COUNTER, VOLTAGE AND TEMPERATURE MEASUREMENT

bq26220
SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
discharge time count registers (DTCH/DTCL)
The DTCH high-byte register (address = 0x68) and the DTCL low-byte register (address = 0x67) determine the
length of time the V_SR < V_SS indicating a discharge. The counts in these registers are incremented at a rate of
4096 counts per hour. If the DTCH/DTCL register continues to count beyond FFFFH, the STD bit is set in the
MODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
Note: If a second rollover occurs, STD is cleared. Access to the bq26220 should be timed to clear DTCH/DTCL
more often than every 170 days. The CLR register forces the reset of both the DTCH and DTCL to zero.
charge-time count registers (CTCH/CTCL)
The CTCH high-byte register (address = 0x66) and the CTCL low-byte register (address = 0x65) determine the
length of time the V_SR >V_SS, indicating a charge activity. The counts in these registers are incremented at a rate
of 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond FFFFH, the STC bit is set in the
MODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
Note: If a second rollover occurs, STC is cleared. Access to the bq26220 should be timed to clear CTCH/CTCL
more often than every 170 days. The CLR register forces the reset of both the CTCH and CTCL to zero.
mode register (MODE)
The MODE register (address 0x64) contains the GPIEN, STAT, STC, STD, POR and wake-up enable
information as described in Table 9.
7
(MSB)
GPIEN
Table 9. MODE Register Values
6
STAT
5
STC
MODE BITS
4
3
STD WOE2
2
WOE1
1
WOE0
0
(LSB)
POR
GPIEN
STAT
STC & STD
WOE[2.0]
POR
Table 10. MODE Register Definitions
GPIEN bit (bit 7) sets the state of the GPIO pin. A 1 configures the GPIO pin as input, while a 0 configures the
GPIO pin as open-drain output. This bit is set to 0 on power-on-reset.
STAT bit (bit 6) sets the state of the open drain output of the GPIO pin (when configured as output by bit 7). A 1
turns off the open drain output while a 0 turns the output on. This bit is set to 1 on power-on-reset.
The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC registers have
rolled over beyond FFFFH. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a DTC rollover.
The wake-up output enable (WOE) bits (bits 3, 2 and 1) indicate the voltage level required between SRP and
SRN so that the bq26220 enters sleep mode after a power down command is issued. Whenever |VSRP − VSRN|
< VWOE, the bq26220 enters sleep mode after the power down command has been issued. On bq26220
power-on-reset these bits are set to 1. Setting all of these bits to zero is valid, but result in immediate sleep.
Refer to Table 3 for the various WOE values.
POR bit (bit 0) indicates a power-on-reset has occurred. This bit is set when VCC has gone below the POR
level. This bit can be also set and cleared by the host, but has no functionality if set by host.
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