BQ26220 Datasheet, PDF (14/19 Pages) Texas Instruments – HIGH PERFORMANCE BATTERY MONITOR IC WITH COULOMB COUNTER, VOLTAGE AND TEMPERATURE MEASUREMENT

bq26220
SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
The serial communication timing specification and illustration sections give the timings for data and break
communication. Communication with the bq26220 always occurs with the least significant bit being transmitted
first. Figure 4 shows an example of a communication sequence to read the bq26220 DCRH register.
BREAK
0
(LSB)
1
COMMAND BYTE
(Written by Host to bq26220)
CMDR=6Eh
2
3
4
5
6
7
(MSB)
0
(LSB)
DATA BYTE (DCRH) = 64h
(Received by Host From bq26220)
1
2
3
4
5
6
7
(MSB)
0
1
1
1
0
1
1
0
MSB
LSB
6Eh=0 1 1 0 1 1 1 0
0
0
1
0
0
1
1
0
MSB
LSB
64h=0 1 1 0 0 1 0 0
Figure 4. bq26220 Communication Sequence
command byte
The command byte of the bq26220 consists of eight contiguous valid command bits. The command byte
contains two fields: W/R Command and address. The W/R bit of the command register determines whether the
command is a read or a write command while the address field containing bit AD6−AD0 indicates the address
to be read or written. The command byte values are shown in Table 7.
Table 7. Command Byte Values
COMMAND BYTE
7
6
5
4
3
2
1
0
W/R AD6 AD5 AD4 AD3 AD2 AD1 AD0
Table 8. Command Byte Definitions
W/R
AD6−AD0
Indicates whether the command byte is a read or write command. A 1 indicates a write command and that the
following eight bits should be written to the register specified by the address field of the command byte, while a
0 indicates that the command is a read. On a read command, the bq26220 outputs the requested register
contents specified by the address field portion of the command byte.
The seven bits labeled AD6−AD0 containing the address portion of the register to be accessed.
bq26220 registers
register maintenance
The host system is responsible for register maintenance. (See Table 4.) To facilitate this maintenance, the
bq26220 clear register (CLR) resets the specific counter or register pair to zero. The host system clears a
register by writing the corresponding register bit to 1. When the bq26220 completes the reset, the corresponding
bit in the CLR register automatically resets to 0, saving the host an extra write/read cycle. Clearing the DTC
register clears the STD bit and sets the DTC count rate to the default value of one count per 0.8789 s. Clearing
the CTC register clears the STC bit and sets the CTC count rate to the default value of one count per 0.8789 s.
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